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Method for calculating warpage of bonded SOI wafer and method for manufacturing bonded SOI wafer
US8962352B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962352-B2 |
| Application number | US-201214240432-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 21, 2012 |
| Priority date | Sep 29, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due to a thickness of the BOX layer of the epitaxial growth SOI wafer; determining a measured value of a warpage of the base wafer before bonding as a warpage C; and calculating a sum of the warpages (A+B+C) as the warpage of the bonded SOI wafer.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for calculating a warpage of a bonded SOI wafer that is fabricated by forming a thermal oxide film on one surface or both surfaces of one of a bond wafer and a base wafer that are formed of silicon single crystal wafers, bonding the bond wafer and the base wafer to each other through the thermal oxide film, then reducing a film thickness of the bond wafer, thereby fabricating an epitaxial growth SOI wafer constituted of a BOX layer on the base…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P74/203Primary
Electricity · mapped topic
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- What does patent US8962352B2 cover?
- A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due…
- Who is the assignee on this patent?
- Yokokawa Isao, Aga Hiroji, Mizusawa Yasushi, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10P74/203. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).