Integrated circuit using deep trench through silicon (DTS)

Patent metadata

Field	Value
Publication number	US-8941211-B2
Application number	US-201313782355-A
Country	US
Kind code	B2
Filing date	Mar 1, 2013
Priority date	Mar 1, 2013
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

First claim

What is claimed is:

1. A radio frequency area of an integrated circuit, comprising:
a substrate having a first resistance, the substrate including an implant region;
a buried oxide layer disposed over the substrate;
an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance;
a silicon layer disposed over the buried oxide layer;
a shallow trench isolation extending from an upper surface…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Cheng Kuo-Yu
• Tsai Wei-Kung
• Tsai Kuan-Chi
• Yang Tsung-Yu
• Chang Chung-Long
• Chen Chun-Hong
• Chao Chih-Ping
• Tang Chen-Yao
• Chen Yu Hung

Classifications

• H10W10/0148

  Electricity · mapped topic

• H10W10/021

  Electricity · mapped topic

• H10W10/20

  Electricity · mapped topic

• H10P90/1908

  Electricity · mapped topic

• H10W10/181

  Electricity · mapped topic