Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar
US-2024419761-A1 · Dec 19, 2024 · US
US8933429B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933429-B2 |
| Application number | US-201313974278-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 23, 2013 |
| Priority date | Mar 14, 2013 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.
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What is claimed is: 1. A selector device for a memory device, the selector device comprising a first layer, wherein the first layer is operable as a first electrode, wherein the first layer comprises a first Fermi level; a second layer disposed above the first layer, wherein the second layer comprises a dielectric or semiconductor layer, wherein the second layer comprises a material having a first band gap, wherein the first band gap has a first conduction band minimum,…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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