Spin transfer torque cell for magnetic random access memory

Patent metadata

Field	Value
Publication number	US-8928100-B2
Application number	US-201113168477-A
Country	US
Kind code	B2
Filing date	Jun 24, 2011
Priority date	Jun 24, 2011
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

First claim

What is claimed is:

1. A spin transfer torque (STT) magnetic random access memory (MRAM) device comprising:
a reference layer configured to have a fixed magnetic moment;
a tunnel barrier layer that is configured to enable electrons to tunnel between the reference layer and a free layer through the tunnel barrier layer;
the free layer, disposed beneath the tunnel barrier layer and configured to have an adaptable magnetic moment for storage of data; and
at least one conductive via disposed beneath the free layer that is connected to an electrode and that has a width that is narrower than a width of the free layer such that a width of at least one active STT area for the storage of data in the free layer is defined by the width of the at least one conductive via.

2. The device of claim 1 , wherein the width of the at least one active STT area is narrower than a width of the reference layer.

3. The device of claim 1 , wherein the device includes a plurality of cells such that each of the conductive vias is included in a different cell and each of the cells is defined by a separate corresponding pillar, wherein each of the pillars includes a separate stack of the reference layer, the tunnel barrier layer and the free layer.

4. The device of claim 1 , wherein at least one of the layers is continuous over a plurality of the conductive vias and wherein the reference layer, the tunnel barrier layer, the free layer and the at least one conductive via are below a bit line.

5. The device of claim 1 , wherein the free layer is directly above the at least one conductive via.

6. The device of claim 1 , wherein a first insulator is disposed between the free layer and the electrode and is lateral to the at least one conductive via and wherein a second insulator or a semiconductor is disposed between the first insulator and the free layer.

7. The device of claim 6 , wherein portions of the free layer that are above the second insulator or the semiconductor are non-conductive and non-magnetic.

8. A computing apparatus comprising:
a spin transfer torque (STT) magnetic random access memory (MRAM) device including
a reference layer configured to have a fixed magnetic moment;
a tunnel barrier layer that is configured to enable electrons to tunnel between the reference layer and a free layer through the tunnel barrier layer;
the free layer, disposed beneath the tunnel barrier layer and configured to have an adaptable magnetic moment for storage of data; and
at least one conductive via disposed beneath the free layer that is connected to an electrode and that has a width that is narrower than a width of the free layer such that a width of at least one active STT area in the free layer for the storage of data is defined by the width of the at least one conductive via; and

a processor configured to utilize the STT MRAM device to perform computations.

9. The apparatus of claim 8 , wherein the free layer is directly above the at least one conductive via.

10. The apparatus of claim 8 , wherein at least one of the layers is continuous over a plurality of the conductive vias.

Assignees

• Gaidis Michael C
• Nowak Janusz J
• Worledge Daniel C
• IBM

Inventors

• Gaidis Michael C
• Nowak Janusz J
• Worledge Daniel C

Classifications

• H01F41/307

  insulating or semiconductive spacer · CPC title

• H01F10/329

  Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H01F10/3254 Primary

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• H01L43/08

  Electricity · mapped topic