Memory device and manufacturing method of the memory device

Patent metadata

Field	Value
Publication number	US-2026068166-A1
Application number	US-202519386016-A
Country	US
Kind code	A1
Filing date	Nov 11, 2025
Priority date	Feb 24, 2021
Publication date	Mar 5, 2026
Grant date	—

Abstract

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.

First claim

What is claimed is:

1 . A memory device comprising:
a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to isolate the first gate stack structure and the second gate stack structure from each other, wherein the slit includes a plurality of holes arranged in a line between the first gate stack structure and the second gate stack structure, and wherein each of the plurality of holes partially overlaps adjacent holes.

2 . The memory device of claim 1 , wherein the slit isolates physically the first gate stack structure and the second gate stack structure.

3 . The memory device of claim 1 , wherein the slit isolates physically the first gate stack structure and the second gate stack structure.

4 . The memory device of claim 1 , wherein the substrate includes a first memory region, a second memory region, and a slit region disposed between the first memory region and the second memory region, and
wherein the first gate stack structure is formed within the first memory region, the second gate stack structure is formed within the second memory region, and the slit is formed within the slit region.

5 . The memory device of claim 4 , wherein the first gate stack structure and the second gate stack structure include a plurality of plate electrodes and a plurality of interlayer insulating layers, which are alternately stacked.

6 . The memory device of claim 5 , wherein the plurality of first holes electrically and physically isolate the plurality of plate electrodes of the first gate stack structure and the plurality of plate electrodes of the second gate stack structure from each other within the slit region.

7 . The memory device of claim 5 , wherein the plurality of interlayer insulating layers of the first gate stack structure and the plurality of interlayer insulating layers of the second gate stack structure extend into the slit region to be connected to each other, and
wherein the plurality of first holes penetrate the plurality of interlayer insulating layers of the first gate stack structure and the plurality of interlayer insulating layers of the second gate stack structure within the slit region.

8 . The memory device of claim 5 , wherein one end portions of the plate electrodes of the first gate stack structure, which are adjacent to the slit, have a first wave pattern.

9 . The memory device of claim 8 , wherein one end portions of the plate electrodes of the second gate stack structure, which are adjacent to the slit, have a second wave pattern.

10 . The memory device of claim 9 , wherein the first wave pattern and the second wave pattern are substantially symmetrical to each other.

11 . The memory device of claim 1 , wherein each of the first gate stack structure and the second gate stack structure includes cell plugs vertically extending toward the substrate.

12 . The memory device of claim 5 , further comprising a source line contact formed at the inside of the slit.

13 . The memory device of claim 12 , further comprising a capping layer disposed between the source line contact and the plurality of plate electrodes.

14 . A memory device comprising:
a first gate stack structure and a second gate stack structure, disposed on a substrate; a slit disposed between the first gate stack structure and the second gate stack structure to isolate the first gate stack structure and the second gate stack structure from each other; and a drain select isolation structure which passes through partially an upper portion of each of the first gate stack structure and the second gate stack structure and extends in the same direction as the slit, wherein the slit includes a plurality of holes arranged in a line between the first gate stack structure and the second gate stack structure, and wherein each of the plurality of holes partially overlaps adjacent holes.

15 . The memory device of claim 14 ,
wherein each of the first gate stack structure and the second gate stack structure is disposed in a memory cell region and in a word line contact region, wherein the memory device further comprises: a plurality of cell plugs which extend in a vertical direction to the first gate stack structure and the second gate stack structure in the memory cell region; and a plurality of contacts which extend within the first gate stack structure and the second gate stack structure in the word line contact region in a vertical direction.

16 . The memory device of claim 14 , wherein the first gate stack structure and the second gate stack structure are electrically or physically isolated by the slit.

17 . The memory device of claim 14 , wherein a sidewall of each of the plurality of holes contacts sidewalls of adjacent holes thereof.

18 . A memory device comprising:
a first gate stack structure disposed in a first memory region and a second gate stack structure disposed in a second memory region; a slit which extends between the first gate stack structure and the second gate stack structure in one direction and isolates the first gate stack structure and the second gate stack structure from each other; a plurality of cell plugs which extend within the first gate stack structure and the second gate stack structure in a vertical direction; a bit line connection structure which is below the first gate stack structure and the second gate stack structure and is connected to the plurality of cell plugs; a first connection structure including a first bonding metal which is connected to the bit line connection structure and has a surface exposed to the outside; a second connection structure including a second bonding metal which contacts the first bonding metal of the first connection structure; and a CMOS circuit structure which is connected to the second connection structure and includes a plurality of transistors, wherein the slit includes a plurality of holes arranged in a line between the first gate stack structure and the second gate stack structure, and wherein a sidewall of each of the plurality of holes contacts sidewalls of adjacent holes thereof.

19 . The memory device of claim 18 , wherein each of the plurality of holes partially overlaps adjacent holes.

20 . The memory device of claim 18 , wherein the plurality of holes isolate physically or electrically the first gate stack structure and the second gate stack structure.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Jang Jung Shik
• Kim Jang Won
• Park Mi Seong

Classifications

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title