Heterogenous integration of semiconductor structures

Patent metadata

Field	Value
Publication number	US-2025391711-A1
Application number	US-202519224361-A
Country	US
Kind code	A1
Filing date	May 30, 2025
Priority date	Jun 21, 2024
Publication date	Dec 25, 2025
Grant date	—

Abstract

Systems, devices, and methods for making semiconductor device assemblies, and more particularly for the heterogenous integration of semiconductor structures, are provided herein. A semiconductor device assembly can include a first semiconductor device bonded to a second semiconductor device. The first semiconductor device can include a first dielectric material having first airgaps and a second dielectric material disposed above the first dielectric material and having second airgaps. The first semiconductor device can also include a first metallization layer embedded in the first dielectric material, a second metallization layer disposed between the first dielectric material and the second dielectric material, a third metallization layer at least partially embedded in the second dielectric material, and one or more first vias extending through the first dielectric material between the first metallization layer and the second metallization layer. Each of the one or more first vias can have an aspect ratio of at least 10.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first dielectric material having a first plurality of airgaps; a first metallization layer embedded in the first dielectric material; a second dielectric material disposed above the first dielectric material and having a second plurality of airgaps; a second metallization layer disposed between the first dielectric material and the second dielectric material; one or more first vias extending through the first dielectric material between the first metallization layer and the second metallization layer, wherein each of the one or more first vias has an aspect ratio of at least 10:1; a third metallization layer at least partially embedded in the second dielectric material, wherein the second metallization layer is disposed between the first metallization layer and the third metallization layer; and one or more second vias extending between the second metallization layer and the third metallization layer.

2 . The semiconductor device of claim 1 , wherein each of the one or more first vias has an aspect ratio of at least 16:1.

3 . The semiconductor device of claim 1 , wherein each of the first metallization layer and the third metallization layer comprises aluminum.

4 . The semiconductor device of claim 1 , wherein the second metallization layer comprises copper.

5 . The semiconductor device of claim 1 , wherein each of the one or more first vias comprises tungsten.

6 . The semiconductor device of claim 1 , wherein the first dielectric material has a thickness of at least 2.2 μm.

7 . The semiconductor device of claim 1 , wherein the first metallization layer comprises first portions and second portions, wherein each of the first portions has a greater cross-sectional dimension than each of the second portions, and wherein the one or more first vias extend only from the second portions, and not the first portions, of the first metallization layer.

8 . The semiconductor device of claim 1 , wherein the third metallization layer comprises first portions and second portions, wherein each of the first portions has a greater cross-sectional dimension than each of the second portions, and wherein the second dielectric material does not extend over the first portions of the third metallization layer.

9 . The semiconductor device of claim 1 , further comprising one or more bond pads embedded in the second dielectric material and one or more third vias extending through the second dielectric material between corresponding ones of the one or more bond pads and the third metallization layer.

10 . A method of making a semiconductor device assembly, the method comprising:
fabricating a first semiconductor device, wherein fabricating comprises:
depositing a first metallization layer on a memory structure;
depositing a first dielectric material on the first metallization layer, wherein depositing the first dielectric material forms a first plurality of airgaps in the first dielectric material;
forming first vias in the first dielectric material, wherein each of the first vias extends from the first metallization layer and has an aspect ratio of at least 10;
depositing a second metallization layer on the first dielectric material such that the first vias extend between the first and second metallization layers;
forming second vias to extend from the second metallization layer;
depositing a third metallization layer above the second metallization layer such that the second vias extend between the second and third metallization layers; and
depositing a second dielectric material on and around the third metallization layer, wherein depositing the second dielectric material forms a second plurality of airgaps in the second dielectric material.

11 . The method of claim 10 , wherein fabricating the first semiconductor device further comprises:
removing portions of the first dielectric material to expose portions of the first metallization layer; probing, via the exposed portions of the first metallization layer, the memory structure; and depositing additional layers of the first dielectric material to bury the first metallization layer and to fully encapsulate the first plurality of airgaps.

12 . The method of claim 11 , wherein fabricating the first semiconductor device further comprises:
prior to forming the first vias in the first dielectric material, planarizing the first dielectric material via chemical mechanical planarization (CMP).

13 . The method of claim 10 , wherein fabricating the first semiconductor device further comprises forming (i) one or more bond pads in the second dielectric material and (ii) one or more third vias that extend between corresponding ones of the bond pads and the third metallization layer.

14 . The method of claim 13 , further comprising:
bonding a second semiconductor device to the one or more bond pads of the first semiconductor device in a face-to-face arrangement; removing portions of the second dielectric material to expose portions of the third metallization layer; and probing, via the exposed portions of the third metallization layer, the semiconductor device assembly.

15 . The method of claim 10 , wherein fabricating the first semiconductor device further comprises:
depositing a passivation layer on the first dielectric material, wherein the passivation layer is deposited in at least some of the first plurality of airgaps; and removing, at least partially, the passivation layer via dry etching or wet etching.

16 . A semiconductor device assembly, comprising:
a first semiconductor device including:
a first dielectric material having a first plurality of airgaps;
a first metallization layer embedded in the first dielectric material;
a second dielectric material disposed above the first dielectric material and having a second plurality of airgaps;
a second metallization layer disposed between the first dielectric material and the second dielectric material;
one or more first vias extending through the first dielectric material between the first metallization layer and the second metallization layer, wherein each of the one or more first vias has an aspect ratio of at least 10;
a third metallization layer at least partially embedded in the second dielectric material, wherein the second metallization layer is disposed between the first metallization layer and the third metallization layer;
one or more second vias extending between the second metallization layer and the third metallization layer; and
one or more bond pads embedded in the second dielectric material; and
a second semiconductor device bonded to the first semiconductor device in a face-to-face arrangement.

17 . The semiconductor device assembly of claim 16 , wherein each of the first metallization layer and the third metallization layer comprises aluminum, wherein each of the second metallization layer and the bond pads comprises copper, and wherein each of the first vias comprises tungsten.

18 . The semiconductor device assembly of claim 16 , wherein the first dielectric material has a thickness of at least 2.2 μm, and wherein each of the first vias has an aspect ratio of at least 16.

19 . The semiconductor device assembly of claim 16 , wherein the second dielectric material has an edge with an etching signature.

20 . The semiconductor device assembly of claim 16 , wherein the third metallization layer comprises first portions and second portions, wherein each of the first portions has a greater cr

Assignees

• Micron Technology Inc

Inventors

• Bhushan Bharat
• Mcdaniel Terrence B
• Kirby Kyle K
• Singh Akshay N
• Parekh Kunal R

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W90/00

  Package configurations · CPC title