Dimension compensation control for directly bonded structures

Patent metadata

Field	Value
Publication number	US-2025372573-A1
Application number	US-202519229922-A
Country	US
Kind code	A1
Filing date	Jun 5, 2025
Priority date	Mar 19, 2020
Publication date	Dec 4, 2025
Grant date	—

Abstract

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

First claim

1 . (canceled)

2 . A method of direct hybrid bonding first and second semiconductor elements, the method comprising:
providing a plurality of first contact features on the first semiconductor element with a first pattern; patterning a plurality of second contact features on the second semiconductor element with a second pattern, the second contact features corresponding to the first contact features; determining an offset of the second pattern with respect to the first pattern; thinning the second semiconductor element to a thickness, the thickness being different than a thickness of the first semiconductor element; and after thinning, direct hybrid bonding the first semiconductor element to the thinned second semiconductor element, including directly bonding nonconductive layers of the first and second semiconductor elements and directly bonding the first contact features with the corresponding second contact features, wherein a lithographic magnification correction factor is applied to the second pattern to mitigate the offset.

3 . The method of claim 2 , further comprising providing a differential expansion compensation structure on the second semiconductor element, the differential expansion compensation structure configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between opposing contact features.

4 . The method of claim 3 , wherein providing the differential expansion compensation structure comprises providing one or more dielectric layers on a back side of the thinned second semiconductor element, the back side opposite the plurality of second contact features, the one or more dielectric layers comprising a compressive layer configured to counterbalance stresses on the nonconductive layer of the second semiconductor element.

5 . The method of claim 3 , wherein the differential expansion compensation structure comprises a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a first dielectric layer on a back side of the thinned second semiconductor element, the back side opposite the plurality of second contact features, and a second dielectric layer on a third semiconductor element, and wherein providing the differential expansion compensation structure comprises directly bonding the second dielectric layer to the first dielectric layer without an adhesive.

6 . The method of claim 3 , wherein the differential expansion compensation structure comprises a plurality of dielectric layers, wherein the plurality of dielectric layers comprises a first dielectric layer and a second dielectric layer, and wherein providing the differential expansion compensation structure comprises providing a metal layer between the first and second dielectric layers.

7 . The method of claim 3 , wherein providing the differential expansion compensation structure comprises diffusing hydrogen ions in the second semiconductor element.

8 . The method of claim 7 , wherein diffusing hydrogen ions comprises exposing the second semiconductor element to a hydrogen-containing plasma.

9 . The method of claim 2 , wherein the first semiconductor element is thicker than the second semiconductor element, the method comprising applying the lithographic magnification correction factor to the first pattern, wherein the application of the lithographic magnification correction factor enlarges the first contact features of the first semiconductor element relative to the corresponding second contact features of the second semiconductor element, and wherein the application of the lithographic magnification correction factor enlarges first spacings between adjacent first contact features relative to corresponding second spacings between adjacent second contact features.

10 . The method of claim 2 , wherein the first semiconductor element is thicker than the second semiconductor element, the method comprising applying the lithographic magnification correction factor to the second pattern, wherein the application of the lithographic magnification correction factor shrinks the second contact features of the second semiconductor element relative to the corresponding first contact features of the first semiconductor element, and wherein the application of the lithographic magnification correction factor shrinks second spacings between adjacent second contact features relative to corresponding first spacings between adjacent first contact features.

11 . The method of claim 2 , further comprising applying the lithographic magnification correction factor to the first pattern and applying a second lithographic magnification correction factor to the second pattern, the second lithographic magnification correction factor different from the lithographic magnification correction factor.

12 . A bonded structure comprising:
a first semiconductor element having a first bonding surface, the first bonding surface including a first contact feature at an inner portion of the first semiconductor element and a second contact feature spaced apart from the first contact feature at a peripheral portion of the first semiconductor element, the first element having a first thickness; and a second semiconductor element having a second bonding surface bonded to the first bonding surface of the first semiconductor element, the second bonding surface having a third contact feature at an inner portion of the second semiconductor element and a fourth contact feature spaced apart from the third contact feature at a peripheral portion of the second semiconductor element, the second semiconductor element having a second thickness, wherein the first contact feature is aligned with and bonded to the third contact feature, wherein the second contact feature is aligned with and bonded to the fourth contact feature, and wherein the first and second contact features are larger than the third and fourth contact features by an amount proportional to a lithographic magnification correction factor F.

13 . The bonded structure of claim 12 , wherein a width of the first contact feature is different than a width of the second contact feature.

14 . The bonded structure of claim 13 , wherein the width of the first contact feature is smaller than the width of the second contact feature.

15 . The bonded structure of claim 12 , wherein a width of the third contact feature is different than a width of the fourth contact feature.

16 . The bonded structure of claim 15 , wherein the width of the third contact feature is smaller than the width of the fourth contact feature.

17 . The bonded structure of claim 12 , wherein the first and second contact features are two of a plurality of contact features, and wherein a pitch between two adjacent contact features of the plurality of contact features is between 0.5 microns and 25 microns.

18 . The bonded structure of claim 17 , wherein the pitch between two adjacent contact features of the plurality of contact features is between 0.5 microns and 5 microns.

19 . The bonded structure of claim 12 , wherein each of the first and second contact features comprise a major lateral dimension between 0.25 microns and 5 microns.

20 . The bonded structure of claim 12 , wherein a width of the first contact feature is no more than 5% larger than a width of the third contact feature.

21 . The bonded structure of claim 12 , wherein, prior to bonding, the first thickness is larger than the second thickness.

22 . The bonded st

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Gao Guilian
• Mirkarimi Laura Wills
• Fountain Jr Gaius Gillman
• Uzoh Cyprian Emeka

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/211

  using auxiliary members, e.g. aids for protecting the bonding area · CPC title