Semiconductor package and method of forming the same

Patent metadata

Field	Value
Publication number	US-2025372491-A1
Application number	US-202418677901-A
Country	US
Kind code	A1
Filing date	May 30, 2024
Priority date	May 30, 2024
Publication date	Dec 4, 2025
Grant date	—

Abstract

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a substrate, a first interposer, a second interposer, a first die, a second die and a bridge die. The first interposer and the second interposer are arranged side by side over the substrate. The first die is disposed on the first interposer. The second die is disposed on the second interposer. The bridge die is disposed on and electrically connected between the first interposer and the second interposer. The first die and the second die are electrically connected to each other through the first interposer, the second interposer and the bridge die.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a substrate; a first interposer and a second interposer arranged side by side over the substrate; a first die disposed on the first interposer; a second die disposed on the second interposer; and a bridge die disposed on and electrically connected between the first interposer and the second interposer, wherein the first die and the second die are electrically connected to each other through the first interposer, the second interposer and the bridge die.

2 . The semiconductor package of claim 1 further comprising an underfill, wherein the bridge die is located between the first die and the second die and overlaps a gap between the first interposer and the second interposer and the gap is filled with the underfill.

3 . The semiconductor package of claim 1 ,
wherein the first interposer comprises:
a first interposer substrate;
a first redistribution structure disposed over the first interposer substrate; and
first conductive connectors disposed on the first redistribution structure and electrically connected to the bridge die, and
wherein the second interposer comprises:
a second interposer substrate;
a second redistribution structure disposed over the second interposer substrate; and
second conductive connectors disposed on the second redistribution structure and electrically connected to the bridge die, wherein a top surface of the first redistribution structure is lower than or higher than a top surface of the second redistribution structure.

4 . The semiconductor package of claim 3 , wherein a level height difference between the top surface of the first redistribution structure and the top surface of the second redistribution structure is less than about 50 μm.

5 . The semiconductor package of claim 3 , wherein a first level height difference between a bottom surface of the bridge die and the top surface of the first redistribution structure is different from a second level height difference between the bottom surface of the bridge die and the top surface of the second redistribution structure.

6 . The semiconductor package of claim 3 further comprising a non-conductive film disposed between the bridge die and the first interposer as well as between the bridge die and the second interposer, wherein the first conductive connectors and the second conductive connectors penetrate through the non-conductive film.

7 . The semiconductor package of claim 6 further comprising a first encapsulant encapsulating the first die and a second encapsulant encapsulating the second die, wherein the first encapsulant further extends between the non-conductive film and the first redistribution structure, and the second encapsulant further extends between the non-conductive film and the second redistribution structure.

8 . The semiconductor package of claim 3 , wherein the first interposer further comprises third conductive connectors disposed on the first redistribution structure and electrically connected to the first die, wherein a height of the first conductive connectors is greater than a height of the third conductive connectors.

9 . A semiconductor package, comprising:
a substrate; a first sub-package on the substrate, and the first sub-package comprising:
a first interposer having a first surface and a second surface opposite to the first surface;
a first die disposed on the first surface of the first interposer;
a first encapsulant disposed on the first surface of the first interposer and encapsulating the first die; and
a first conductive terminal disposed between the second surface of the first interposer and the substrate;
a second sub-package arranged side by side with the first sub-package on the substrate, and the second sub-package comprising:
a second interposer having a third surface and a fourth surface opposite to the fourth surface;
a second die disposed on the third surface of the second interposer;
a second encapsulant disposed on the third surface of the second interposer and encapsulating the second die; and
a second conductive terminal disposed between the fourth surface of the second interposer and the substrate; and
a bridge die disposed over the first encapsulant and the second encapsulant, wherein the bridge die is electrically connected with the first interposer and the second interposer, wherein a standoff of the first conductive terminal is different from a standoff of the second conductive terminal.

10 . The semiconductor package of claim 9 , wherein the first sub-package has a first region and a second region, the first die is located in the first region and a portion of the bridge die is located in the second region, the first encapsulant has a first thickness in the first region and a second thickness in the second region, and the first thickness is greater than the second thickness.

11 . The semiconductor package of claim 10 , wherein the second sub-package has a third region and a fourth region, the second die is located in the fourth region and another portion of the bridge die is located in the third region, the second encapsulant has a third thickness in the third region and the third thickness is different from the second thickness.

12 . The semiconductor package of claim 11 , wherein a top surface of the first encapsulant in the second region substantially levels with a top surface of the second encapsulant in the third region, and a top surface of the first encapsulant in the first region does not level with a top surface of the second encapsulant in the fourth region.

13 . The semiconductor package of claim 9 further comprising a filling material disposed between the first interposer and the second interposer as well as between the first encapsulant and the second encapsulant, wherein the bridge die comprises a first conductive connector partially disposed in the first encapsulant and a second conductive connector partially disposed in the second encapsulant.

14 . The semiconductor package of claim 13 , wherein the filling material further extends to a first gap between the second surface of the first interposer and the substrate and a second gap between the fourth surface of the second interposer and the substrate.

15 . A method for forming a semiconductor package, comprising:
placing a first sub-package and a second sub-package to a substrate, wherein the first sub-package and the second sub-package are arranged side by side, the first sub-package comprises a first interposer, a first die disposed on the first interposer and a first encapsulant disposed on the first interposer and encapsulating the first die, and the second sub-package comprises a second interposer, a second die disposed on the second interposer and a second encapsulant disposed on the second interposer and encapsulating the second die; filling an insulating material into a gap between the first sub-package and the second sub-package; forming a cavity to expose first conductive connectors of the first interposer and second conductive connectors of the second interposer; and disposing a bridge die in the cavity to electrically connect with the first interposer and the second interposer by the first conductive connectors and the second conductive connectors.

16 . The method of claim 15 , wherein forming the cavity comprises:
removing a portion of the first encapsulant, a portion of the second encapsulant and a portion of the insulating material until the first conductive connectors and the second conductive connectors are exposed, wherein a bottom surface of the cavity level

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Wong Cheng-Shiuan
• Chiu Chao-Wei
• Chen Hsin Liang
• Kuo Hsuan-Ting
• Pei Hao-Jan
• Lin Hsiu-Jen
• Cheng Chia-Shen
• Chen Cheng-Ting
• Shih Hao-Jan
• Tsao Chih-Chiang

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title