Emission selection driver, emission selection gate driver including the same, and an electronic device including the emission selection gate driver

Patent metadata

Field	Value
Publication number	US-2025342807-A1
Application number	US-202519023006-A
Country	US
Kind code	A1
Filing date	Jan 15, 2025
Priority date	May 2, 2024
Publication date	Nov 6, 2025
Grant date	—

Abstract

An emission selection driver includes an emission driver configured to output an emission signal in response to a voltage of an emission control node and a voltage of an inverted emission control node and a selection driver configured to output a selection signal based on the voltage of the emission control node, the voltage of the inverted emission control node, and an enable signal.

First claim

What is claimed is:

1 . An emission selection driver comprising:
an emission driver configured to output an emission signal in response to a voltage of an emission control node and a voltage of an inverted emission control node; and a selection driver configured to output a selection signal based on the voltage of the emission control node, the voltage of the inverted emission control node, and an enable signal.

2 . The emission selection driver of claim 1 , wherein the enable signal is a global scan signal, and the emission signal and the selection signal are progressive scan signals.

3 . The emission selection driver of claim 1 , wherein the voltage of the emission control node has a phase opposite to the voltage of the inverted emission control node, and
wherein the emission signal has a same phase as the voltage of the emission control node.

4 . The emission selection driver of claim 1 , wherein, when a pulse of the enable signal overlaps a pulse of the emission signal, a pulse of the selection signal is output.

5 . The emission selection driver of claim 1 , wherein, when a pulse of the enable signal is output before a pulse of the emission signal and the pulse of the enable signal partially overlaps with the pulse of the emission signal, the selection signal has no pulse.

6 . The emission selection driver of claim 1 , wherein, when the enable signal maintains a first level, a pulse of the selection signal is output.

7 . The emission selection driver of claim 1 , wherein, when a pulse of the enable signal is output later than a pulse of the emission signal and the pulse of the enable signal partially overlaps with the pulse of the emission signal, a pulse of the selection signal is output.

8 . The emission selection driver of claim 1 , wherein a pulse of the selection signal has a same length and timing as a pulse of the emission signal.

9 . The emission selection driver of claim 1 , wherein the selection driver comprises:
a first selection transistor comprising a gate electrode configured to receive the voltage of the emission control node, a first electrode configured to receive the enable signal, and a second electrode; a second selection transistor comprising a gate electrode connected to the second electrode of the first selection transistor, a first electrode configured to receive the voltage of the inverted emission control node, and a second electrode connected to a selection control node; a third selection transistor comprising a gate electrode configured to receive the voltage of the emission control node, a first electrode configured to receive a high gate voltage, and a second electrode connected to the selection control node; a fourth selection transistor comprising a gate electrode connected to the selection control node, a first electrode configured to receive the high gate voltage, and a second electrode connected to a selection output node from which the selection signal is output; and a fifth selection transistor comprising a gate electrode configured to receive the voltage of the emission control node, a first electrode configured to receive a low gate voltage, and a second electrode connected to the selection output node.

10 . The emission selection driver of claim 9 , wherein the first to fifth selection transistors are P-type transistors.

11 . The emission selection driver of claim 9 , wherein the selection driver further comprises:
a selection capacitor comprising a first electrode configured to receive the high gate voltage and a second electrode connected to the selection control node.

12 . The emission selection driver of claim 9 , wherein, when the voltage of the emission control node has a first level, the voltage of the inverted emission control node has a second level, and the enable signal has the first level, the selection signal has the first level.

13 . The emission selection driver of claim 9 , wherein, when the voltage of the emission control node has a first level, the voltage of the inverted emission control node has a second level, and the enable signal has the second level, the selection signal has the first level.

14 . The emission selection driver of claim 9 , wherein, when the voltage of the emission control node has a second level and the voltage of the inverted emission control node has a first level, a voltage of the gate electrode of the second selection transistor maintains a previous state.

15 . The emission selection driver of claim 14 , wherein, when the previous state of the voltage of the gate electrode of the second selection transistor is the first level, the selection signal has the second level.

16 . The emission selection driver of claim 14 , wherein, when the previous state of the voltage of the gate electrode of the second selection transistor is the second level, a voltage of the selection control node maintains a previous state.

17 . The emission selection driver of claim 16 , wherein, when the previous state of the voltage of the selection control node is the second level, the selection signal maintains the previous state.

18 . An emission selection gate driver comprising:
an emission driver configured to output an emission signal in response to a voltage of an emission control node and a voltage of an inverted emission control node; a selection driver configured to output a selection signal based on the voltage of the emission control node, the voltage of the inverted emission control node, and an enable signal; and a gate driver configured to output a gate signal which is masked based on the selection signal.

19 . The emission selection gate driver of claim 18 , wherein the enable signal is a global scan signal, and the emission signal and the selection signal are progressive scan signals.

20 . The emission selection gate driver of claim 18 , wherein the emission selection driver comprises:
a first selection transistor comprising a gate electrode configured to receive the voltage of the emission control node, a first electrode configured to receive the enable signal, and a second electrode; a second selection transistor comprising a gate electrode connected to the second electrode of the first selection transistor, a first electrode configured to receive the voltage of the inverted emission control node, and a second electrode connected to a selection control node; a third selection transistor comprising a gate electrode configured to receive the voltage of the emission control node, a first electrode configured to receive a high gate voltage, and a second electrode connected to the selection control node; a fourth selection transistor comprising a gate electrode connected to the selection control node, a first electrode configured to receive the high gate voltage, and a second electrode connected to a selection output node from which the selection signal is output; and a fifth selection transistor comprising a gate electrode configured to receive the voltage of the emission control node, a first electrode configured to receive a low gate voltage, and a second electrode connected to the selection output node.

21 . An electronic device comprising a display device having an emission selection driver to drive the display device, the emission selection driver comprising:
an emission driver configured to output an emission signal in response to a voltage of an emission control node and a voltage of an inverted emission control node; and a selection driver configured to output a

Assignees

• Samsung Display Co Ltd

Inventors

• Yun Eseudeo
• Keum Nackhyeon
• Kim Kyung-Hoon
• Kim Yongchan

Classifications

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title

• G09G2310/0205

  Simultaneous scanning of several lines in flat panels · CPC title