Emission control driver and display device having the same

Patent metadata

Field	Value
Publication number	US-10453386-B2
Application number	US-201715603997-A
Country	US
Kind code	B2
Filing date	May 24, 2017
Priority date	May 25, 2016
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

An emission control driver includes a plurality of stages. Each stage includes three circuit blocks and two output transistors. A first circuit block generates first and second control signals based on a first clock signal and a start signal or carry signal. A second circuit block controls the voltage level of the first control signal based on the first control signal and a second clock signal. A third circuit block generates a third control signal based on the second control signal and the second clock signal. The first output transistor outputs a first voltage as an emission control signal based on the first control signal. A second output transistor outputs a second voltage as the emission control signal based on the third control signal. The second circuit block maintains the voltage level of the first control signal while the first output transistor is turned off.

First claim

What is claimed is:

1. An emission control driver, comprising:
a plurality of stages, each of the stages including:
a first circuit block to generate a first control signal and a second control signal based on a first clock signal and a start signal or a carry signal;
a second circuit block to control a voltage level of the first control signal based on the first control signal and a second clock signal, the second circuit block including:
a first switching transistor to turn on or turn off based on the first control signal, the first switching transistor coupled between a second clock signal providing line and a third node; and
a first capacitor coupled between a first node and the third node;

a third circuit block to generate a third control signal based on the second control signal and the second clock signal;
a first output transistor to output a first voltage as an emission control signal based on the first control signal provided to a first output node; and
a second output transistor to output a second voltage as the emission control signal based on the third control signal provided to a second output node, wherein the second circuit block is to maintain a voltage level of the first control signal while the first output transistor is turned off.

2. The emission control driver as claimed in claim 1 , wherein the first circuit block includes:
a second switching transistor to turn on or turn off based on the first clock signal, the second switching transistor coupled between a first node and a start signal providing line or a carry signal providing line;
a third switching transistor to turn on or turn off based on a voltage of the first node, the third switching transistor coupled between a first clock signal providing line and a second node; and
a fourth switching transistor to turn on or turn off based on the first clock signal, the fourth switching transistor coupled between a first voltage providing line and the second node.

3. The emission control driver as claimed in claim 2 , wherein:
the voltage of the first node is to be provided to the second circuit block as the first control signal, and
a voltage of the second node is to be provided to the third circuit block as the second control signal.

4. The emission control driver as claimed in claim 1 , wherein the second circuit block includes a fifth switching transistor coupled between the third node and a second voltage providing line.

5. The emission control driver as claimed in claim 4 , wherein the fifth switching transistor is to turn on or turn off based on the second control signal.

6. The emission control driver as claimed in claim 4 , wherein the fifth switching transistor is to turn on or turn off based on the third control signal.

7. The emission control driver as claimed in claim 4 , wherein the second circuit block includes:
a sixth switching transistor to turn on or turn off based on the second clock signal, the sixth switching transistor coupled between the first node and a fourth node; and
a seventh switching transistor to turn on or turn off based on the second control signal, the seventh switching transistor coupled between the fourth node and a second voltage providing line.

8. The emission control driver as claimed in claim 1 , wherein the third circuit block includes:
a fifth switching transistor to turn on or turn off based on the second control signal, the fifth switching transistor coupled between a fifth node and a second clock signal providing line;
a second capacitor coupled between a second node and a fifth node;
a sixth switching transistor to turn on or turn off based on the first control signal, the sixth switching transistor coupled between a second voltage providing line and the second output node;
a seventh switching transistor to turn on or turn off based on the first control signal, the seventh switching transistor coupled between a second voltage providing line and the second output node; and
a third capacitor coupled between the second voltage providing line and the second output node.

9. The emission control driver as claimed in claim 1 , wherein the first clock signal and the second clock signal have a same period.

10. A display device, comprising:
a display panel including a plurality of pixels;
a scan driver to provide scan signals to the pixels;
a data driver to provide data signals to the pixels;
an emission control driver including a plurality of stages to provide emission control signals to the pixels; and
a timing controller to generate control signals to control the scan driver, the data driver, and the emission control driver, wherein each of the stages includes:
a first circuit block to generate a first control signal and a second control signal based on a first clock signal and a start signal or a carry signal;
a second circuit block to control a voltage level of the first control signal based on the first control signal and a second clock signal, the second circuit block including:
a first switching transistor to turn on or turn off based on the first control signal, the first switching transistor coupled between a second clock signal providing line and a third node, and
a first capacitor coupled between a first node and the third node;

a third circuit block to generate a third control signal based on the second control signal and the second clock signal;
a first output transistor to output a first voltage as an emission control signal based on the first control signal provided to a first output node; and
a second output transistor to output a second voltage as the emission control signal based on the third control signal provided to a second output node, wherein the second circuit block is to maintain a voltage level of the first control signal while the first output transistor is turned off.

11. The display device as claimed in claim 10 , wherein the first circuit block includes:
a second switching transistor to turn on or turn off based on the first clock signal, the second switching transistor coupled between a first node and a start signal providing line or a carry signal providing line;
a third switching transistor to turn on or turn off based on a voltage of the first node, the third switching transistor coupled between a first clock providing line and a second node; and
a fourth switching transistor to turn on or turn off based on the first clock signal, the fourth switching transistor coupled between a first voltage providing line and the second node.

12. The display device as claimed in claim 11 , wherein:
the voltage of the first node is to be provided to the second circuit block as a first control signal, and
the voltage of the second node is to be provided to the third circuit block as a second control signal.

13. The display device as claimed in claim 10 , wherein the second circuit block includes a fifth switching transistor coupled between the third node and a second voltage providing line.

14. The display device as claimed in claim 13 , wherein the fifth switching transistor is to turn on or turn off based on the second control signal.

15. The display device as claimed in claim 13 , wherein the fifth switching transistor is to turn on or turn off based on the third control signal.

16. The display device as claimed in claim 10 , wherein the second circuit block includes:
a sixth switching transistor to turn on or turn off based on the second clock signal, the sixth switching transistor coupled between the first node and a fourth node; and
a seventh switching transistor to turn on or turn off based on the second contro

Assignees

• Samsung Display Co Ltd

Inventors

• Jang Hwan-Soo

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title