Scan driver and display device

Patent metadata

Field	Value
Publication number	US-11244629-B2
Application number	US-202016888465-A
Country	US
Kind code	B2
Filing date	May 29, 2020
Priority date	Oct 11, 2019
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A scan driver includes: a plurality of stages, each stage including: a logic circuit configured to transfer an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal that is provided as the input signal for a next stage in response to a voltage of the bootstrapped first node; and a masking controller configured to receive a masking signal and the carry signal, and to output the masking signal as a scan signal provided to a pixel row corresponding to the each stage in response to the carry signal.

First claim

What is claimed is:

1. A scan driver comprising:
a plurality of stages, each stage comprising:
a logic circuit configured to transfer an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal;
a carry output circuit configured to output the second clock signal as a carry signal that is provided as the input signal for a next stage in response to a voltage of the bootstrapped first node; and
a masking controller configured to receive a masking signal and the carry signal, and to output the masking signal as a scan signal provided to a pixel row corresponding to the each stage in response to the carry signal, wherein the masking controller includes:
a first transistor including a gate configured to receive the carry signal, a first terminal coupled to a scan output node at which the scan signal is output, and a second terminal configured to receive the masking signal.

2. The scan driver of claim 1 , wherein the masking controller includes:
a second transistor including a gate coupled to a second node, a first terminal configured to receive a gate off voltage, and a second terminal coupled to the scan output node.

3. The scan driver of claim 1 , wherein the carry output circuit includes:
a third transistor including a gate coupled to the first node, a first terminal coupled to a carry output node at which the carry signal is output, and a second terminal configured to receive the second clock signal; and
a fourth transistor including a gate coupled to a second node, a first terminal configured to receive a gate off voltage, and a second terminal coupled to the carry output node.

4. The scan driver of claim 1 , wherein the masking signal has an on level or an off level according to a driving frequency of a panel region including the pixel row in a first active period of the carry signal, and
wherein the masking controller is configured to output the scan signal having the on level when the masking signal has the on level, and to output the scan signal having the off level when the masking signal has the off level.

5. The scan driver of claim 4 , wherein a second active period of the masking signal in which the masking signal has the on level at least partially overlaps the first active period of the carry signal.

6. The scan driver of claim 5 , wherein an end time point of the second active period of the masking signal leads an end time point of the first active period of the carry signal.

7. The scan driver of claim 1 , wherein the logic circuit includes:
an input circuit configured to transfer the input signal to a third node in response to the first clock signal;
a stress relaxing circuit between the first node and the third node, and configured to transfer the input signal from the third node to the first node such that the voltage of the first node is changed to a first on level;
a bootstrap circuit configured to change the voltage of the first node from the first on level to a second on level by bootstrapping the first node based on the second clock signal, the second on level having an absolute value greater than an absolute value of the first on level;
a holding circuit configured to hold a second node as an off level while the carry signal is output; and
a stabilizing circuit configured to periodically apply a gate on voltage to the second node in response to the second clock signal, and to periodically apply a gate off voltage to the third node in response to the first clock signal after the carry signal is output.

8. The scan driver of claim 7 , wherein the input circuit includes:
a fifth transistor including a gate configured to receive the first clock signal, a first terminal configured to receive the input signal, and a second terminal coupled to the third node.

9. The scan driver of claim 7 , wherein the stress relaxing circuit includes:
a sixth transistor including a gate configured to receive the gate on voltage, a first terminal coupled to the third node, and a second terminal coupled to the first node.

10. The scan driver of claim 7 , wherein the bootstrap circuit includes:
a first capacitor including a first electrode coupled to a carry output node at which the carry signal is output, and a second electrode coupled to the first node.

11. The scan driver of claim 7 , wherein the holding circuit includes:
a seventh transistor including a gate coupled to the third node, a first terminal coupled to the second node, and a second terminal configured to receive the first clock signal.

12. The scan driver of claim 7 , wherein the stabilizing circuit includes:
an eighth transistor including a gate configured to receive the first clock signal, a first terminal coupled to the second node, and a second terminal configured to receive the gate on voltage;
a ninth transistor including a gate coupled to the second node, a first terminal configured to receive the gate off voltage, and a second terminal;
a tenth transistor including a gate configured to receive the second clock signal, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the third node; and
a second capacitor including a first electrode configured to receive the gate off voltage, and a second electrode coupled to the second node.

13. A scan driver comprising:
a plurality of stages, each stage comprising:
a first transistor including a gate coupled to a carry output node, a first terminal coupled to a scan output node, and a second terminal configured to receive a masking signal;
a second transistor including a gate coupled to a second node, a first terminal configured to receive a gate off voltage, and a second terminal coupled to the scan output node;
a third transistor including a gate coupled to a first node, a first terminal coupled to the carry output node, and a second terminal configured to receive a second clock signal;
a fourth transistor including a gate coupled to the second node, a first terminal configured to receive the gate off voltage, and a second terminal coupled to the carry output node;
a fifth transistor including a gate configured to receive a first clock signal, a first terminal configured to receive an input signal, and a second terminal coupled to a third node;
a sixth transistor including a gate configured to receive a gate on voltage, a first terminal coupled to the third node, and a second terminal coupled to the first node;
a first capacitor including a first electrode coupled to the carry output node, and a second electrode coupled to the first node;
a seventh transistor including a gate coupled to the third node, a first terminal coupled to the second node, and a second terminal configured to receive the first clock signal;
an eighth transistor including a gate configured to receive the first clock signal, a first terminal coupled to the second node, and a second terminal configured to receive the gate on voltage;
a ninth transistor including a gate coupled to the second node, a first terminal receiving the gate off voltage, and a second terminal;
a tenth transistor including a gate configured to receive the second clock signal, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the third node; and
a second capacitor including a first electrode configured to receive the gate off voltage, and a second electrode coupled to the second node,
wherein the masking signal has an on level or an off level according to a driving frequency of a panel region including a pixel row in a first active period of a carry signal, and
wherein the f

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Seong Heon
• Seo Hae-Kwan

Classifications

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3208 Primary

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title