Shift register unit, driving method, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-11232734-B2
Application number	US-201916964465-A
Country	US
Kind code	B2
Filing date	Sep 25, 2019
Priority date	Sep 25, 2019
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes a first gate driving output circuit and a second gate driving output circuit. The first gate driving output circuit is used to output a first gate driving signal through the first gate driving signal output terminal; the second gate driving output circuit is used to generate a second gate driving signal outputted simultaneously with the first gate driving signal based on the first gate driving signal, a first clock signal and a second clock signal. In the present disclosure, the second gate driving output circuit is added, the first gate driving signal, the first clock signal, and the second clock signal are used to generate an inverted second gate driving signal, so that positive and negative switching control signals are generated by one stage of shift register unit.

First claim

What is claimed is:

1. A shift register unit, comprising:
a first gate driving output circuit; and
a second gate driving output circuit,
wherein the first gate driving output circuit is configured to output a first gate driving signal through a first gate driving signal output terminal,
wherein the second gate driving output circuit is configured to generate a second gate driving signal based on the first gate driving signal, a first clock signal, and a second clock signal, and
wherein the second gate driving circuit comprises:
a first pull-down node control circuit;
a pull-down circuit; and
an output control circuit, the output control circuit being used to control connection or disconnection between a second gate driving signal output terminal and a first voltage terminal under the control of the first gate driving signal.

2. The shift register unit according to claim 1 , wherein the first gate driving signal and the second gate driving signal are inverted in phase.

3. The shift register unit according to claim 1 , wherein
the first pull-down node control circuit is used to control a potential of a first pull-down node under the control of the first gate driving signal, the first clock signal, and the second clock signal; and
the pull-down circuit is used to control connection or disconnection between the second gate driving signal output terminal and a second voltage terminal under the control of the potential of the first pull-down node.

4. The shift register unit according to claim 3 , wherein the first pull-down node control circuit is electrically connected to a first gate driving signal output terminal, the first clock signal terminal, the second clock signal terminal, the first pull-down node, the first voltage terminal and a third voltage terminal, and is configured to control connection or disconnection between the first pull-down node and the first voltage terminal under the control of the first gate driving signal, control connection or disconnection between the first pull-down node and the third voltage terminal under the control of the first clock signal, and control the potential of the first pull-down node based on the second clock signal.

5. The shift register unit according to claim 3 , wherein the first pull-down node control circuit is further configured to control the potential of the first pull-down node based on the second gate driving signal.

6. The shift register unit according to claim 3 , wherein the first pull-down node control circuit comprises a first pull-down node control transistor, a second pull-down node control transistor, and a first pull-down node control capacitor,
a control electrode of the first pull-down node control transistor is electrically connected to the first gate driving signal output terminal, and a first electrode of the first pull-down node control transistor is electrically connected to the first voltage terminal, and a second electrode of the first pull-down node control transistor is electrically connected to the first pull-down node;
a control electrode of the second pull-down node control transistor is electrically connected to the first clock signal terminal, a first electrode of the second pull-down node control transistor is electrically connected to the first pull-down node, and a second electrode of the second pull-down node control transistor is electrically connected to the third voltage terminal; and
a first terminal of the first pull-down node control capacitor is electrically connected to the first pull-down node, and a second terminal of the first pull-down node control capacitor is electrically connected to the second clock signal terminal.

7. The shift register unit according to claim 5 , wherein the first pull-down node control circuit further comprises a second pull-down node control capacitor,
a first terminal of the second pull-down node control capacitor is electrically connected to the first pull-down node, and a second terminal of the second pull-down node control capacitor is electrically connected to the second gate driving signal output terminal.

8. The shift register unit according to claim 1 , wherein the output control circuit comprises an output control transistor,
a control electrode of the output control transistor is electrically connected to the first gate driving signal output terminal, a first electrode of the output control transistor is electrically connected to the first voltage terminal, and a second electrode of the output control transistor is electrically connected to the second gate driving signal output terminal.

9. The shift register unit according to claim 8 , wherein the output control transistor comprises a first transistor and a second transistor,
a control electrode of the first transistor is electrically connected to a control electrode of the second transistor, a first electrode of the first transistor is the first electrode of the output control transistor, a second electrode of the first transistor is electrically connected to a first electrode of the second transistor, a second electrode of the second transistor is the second electrode of the output control transistor.

10. The shift register unit according to claim 8 , wherein the control electrode of the output control transistor comprises a top gate and a bottom gate electrically connected to each other.

11. The shift register unit according to claim 3 , wherein the pull-down circuit comprises a pull-down transistor,
a control electrode of the pull-down transistor is electrically connected to the first pull-down node, a first electrode of the pull-down transistor is electrically connected to the second gate driving signal output terminal, and a second electrode of the pull-down transistor is electrically connected to the second voltage terminal.

12. The shift register unit according to claim 11 , wherein the control electrode of the pull-down transistor comprises a top gate and a bottom gate electrically connected to each other.

13. A shift register unit, comprising:
a first gate driving output circuit; and
a second gate driving output circuit,
wherein the first gate driving output circuit is configured to output a first gate driving signal through a first gate driving signal output terminal,
wherein the second gate driving output circuit is configured to generate a second gate driving signal based on the first gate driving signal, a first clock signal, and a second clock signal,
wherein the first gate driving output circuit is used to control to output the first gate driving signal under the control of the third clock signal and the fourth clock signal,
wherein the first pull-down node control circuit includes a first pull-down node control transistor, a second pull-down node control transistor, a first pull-down node control capacitor, and a second pull-down node control capacitor, and the pull-down circuit includes a pull-down transistor,
wherein a control electrode of the first pull-down node control transistor is electrically connected to the first gate driving signal output terminal, and a first electrode of the first pull-down node control transistor is electrically connected to the first voltage terminal, and a second electrode of the first pull-down node control transistor is electrically connected to the first pull-down node,
wherein a control electrode of the second pull-down node control transistor is electrically connected to the first clock signal terminal, a first electrode of the second pull-down node control transistor is electrically connected to the first pull-down node, and a second electrode of the second pull-down node control transistor is electric

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shang Guangliang
• Zheng Can
• Lu Jiangnan
• Dong Tian
• Liu Libin
• Han Long
• Shi Shiming
• Wang Dawei

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title