Memory device and operation method thereof

Patent metadata

Field	Value
Publication number	US-2025311242-A1
Application number	US-202418624605-A
Country	US
Kind code	A1
Filing date	Apr 2, 2024
Priority date	Mar 26, 2024
Publication date	Oct 2, 2025
Grant date	—

Abstract

A semiconductor device and method for forming thereof is provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes memory cells each having a vertical transistor and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor layer extending along a vertical direction and a gate structure coupled to the semiconductor layer. A leakage value of the semiconductor layer is lower than a pico-ampere. The first semiconductor structure is bonded with the second semiconductor structure, and the vertical transistor is between the peripheral circuit and the storage unit.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first semiconductor structure comprising a peripheral circuit; and a second semiconductor structure comprising memory cells each having a vertical transistor and a storage unit coupled to the vertical transistor, and the vertical transistor comprising a semiconductor layer extending along a vertical direction and a gate structure coupled to the semiconductor layer; wherein a leakage value of the semiconductor layer is lower than a pico-ampere; and the first semiconductor structure is coupled with the second semiconductor structure, and the vertical transistor is between the peripheral circuit and the storage unit.

2 . The semiconductor device of claim 1 , wherein the second semiconductor structure further comprises:
bit lines each extending along a first lateral direction and coupled with the semiconductor layer; and gate lines each extending along a second lateral direction and coupled with the gate structure, wherein the vertical direction, the first lateral direction, and the second lateral direction are perpendicular to each other.

3 . The semiconductor device of claim 2 , wherein the bit lines are between the vertical transistors and the peripheral circuit.

4 . The semiconductor device of claim 2 , wherein each bit line is coupled with at least two opposite sides of an end of the semiconductor layer of each vertical transistor away from the storage unit.

5 . The semiconductor device of claim 1 , wherein the gate structure comprises a gate electrode and a gate dielectric between the gate electrode and the semiconductor layer in the first and second lateral directions.

6 . The semiconductor device of claim 1 , wherein the vertical transistor is a single-gate transistor in which a gate structure of the vertical transistor is located at one side of the semiconductor layer in a plan view.

7 . The semiconductor device of claim 6 , wherein the semiconductor layer comprises:
a vertical portion extending along the vertical direction; and an extending portion extending from an end of the vertical portion towards an adjacent vertical transistor along a second lateral direction; wherein the extending portion is coupled with the storage unit; and the vertical direction and the second lateral direction are perpendicular to each other.

8 . The semiconductor device of claim 1 , wherein the vertical transistor comprises a double-gate transistor in which a gate structure of the vertical transistor is located at two opposite sides of the semiconductor layer.

9 . The semiconductor device of claim 8 , wherein the semiconductor layer comprises:
a vertical portion extending along the vertical direction; and an extending portion extending from an end of the vertical portion towards two adjacent vertical transistors along a second lateral direction; wherein the extending portion is coupled with the storage unit; and the vertical direction and the second lateral direction are perpendicular to each other.

10 . The semiconductor device of claim 1 , wherein the vertical transistor comprises a gate-all-around (GAA) transistor in which the gate structure fully surrounds the semiconductor layer in a plan view.

11 . The semiconductor device of claim 10 , wherein the semiconductor layer comprises:
a vertical portion extending along the vertical direction; and an extending portion extending from an end of the vertical portion towards two adjacent vertical transistors along a second lateral direction; wherein the extending portion is coupled with the storage unit; and the vertical direction and the second lateral direction are perpendicular to each other.

12 . The semiconductor device of claim 1 , wherein the vertical transistor comprises a tri-gate transistor in which the gate structure partially surrounds the semiconductor layer in a plan view.

13 . The semiconductor device of claim 1 , wherein the second semiconductor structure further comprises a pad-out interconnect layer, and the storage units are disposed between the vertical transistors and the pad-out interconnect layer.

14 . The semiconductor device of claim 1 , wherein the first semiconductor structure further comprises a pad-out interconnect layer, and the peripheral circuit is disposed between the second semiconductor structure and the pad-out interconnect layer.

15 . The semiconductor device of claim 1 , wherein the semiconductor layer comprises one or a combination of In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, and In x Ga y O.

16 . A method for forming a semiconductor memory device, comprising:
forming a first set of memory cells on a substrate; forming a dielectric layer covering the first set of memory cells; and forming a second set of memory cells on the dielectric layer; wherein each of the memory cells of the first set and the second set comprises a vertical transistor and a storage unit coupled to the vertical transistor, the vertical transistor comprises a semiconductor layer extending along a vertical direction and a gate structure coupled to the semiconductor layer; and a leakage value of the semiconductor layer is lower than a pico-ampere.

17 . The method of claim 16 , further comprising:
coupling a peripheral circuit with the second set of memory cells, wherein the vertical transistors of the second set of memory cells are between the peripheral circuit and the storage units of the second set of memory cells.

18 . The method of claim 17 , wherein forming the first set of memory cells comprises:
forming the storage units on the substrate, wherein the storage units are surrounded by a first isolation layer; forming a second isolation layer covering the storage units; forming through holes on the second isolation layer to expose the storage units; and forming the vertical transistors in the through holes.

19 . The method of claim 18 , wherein forming the vertical transistors in the through holes comprises:
forming two semiconductor layers of two adjacent vertical transistors on two opposite sidewalls of each of the through holes, wherein comprises:
epitaxially growing an initial semiconductor layer covering a bottom and the two opposite sidewalls of each of the through hole; and
forming a trench on the initial semiconductor layer on the bottom of the through hole to punch through the initial semiconductor layer into two separate semiconductor layers of two adjacent vertical transistors;
forming two gate structures coupled to the two semiconductor layers respectively; and filling the through holes with dielectric materials to isolate the two gate structures from each other.

20 . A semiconductor device, comprising:
a first semiconductor structure comprising a peripheral circuit; and a second semiconductor structure comprising a first set of memory cells and a second set of memory cells stacked on the first set of memory cells; wherein each of the memory cells of the first set and the second set comprises a vertical transistor and a storage unit coupled to the vertical transistor, the vertical transistor comprises a semiconductor layer extending along a vertical direction and a gate structure coupled to the semiconductor layer, and a leakage value of the semiconductor layer is lower than a pico-ampere; and the first semiconductor structure is bonded with the second semi

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Liu Yaqin
• Liu Wei
• Chen Liang
• Xia Zhiliang
• Huo Zongliang
• Yang Yuancheng
• Zhao Dongxue

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title