Method for patterning for chemical mechanical polishing (cmp) iso-dense bias compensation using z-height

Patent metadata

Field	Value
Publication number	US-2025300010-A1
Application number	US-202418611009-A
Country	US
Kind code	A1
Filing date	Mar 20, 2024
Priority date	Mar 20, 2024
Publication date	Sep 25, 2025
Grant date	—

Abstract

Aspects of the present disclosure provide a method for chemical mechanical polishing (CMP) iso-dense bias compensation using z-height. For example, the method can include forming a dielectric material on a substrate within a first region to form one or more first dielectric layers that are spaced from one another, and forming on a first one of the first dielectric layers a first height correction layer that has a first height that is determined based on a first pattern density of the first region. The method can also include depositing a conductive material on the substrate to fill one or more first trenches surrounded by the first dielectric layers and the first height correction layer and cover the first dielectric layers and the first height correction layer, and performing a planarization process to planarize the conductive material and the first height correction layer until uncovering the first dielectric layers.

First claim

What is claimed is:

1 . A method, comprising:
forming a dielectric material on a substrate within a first region to form one or more first dielectric layers that are spaced from one another; forming a first height correction layer on a first one of the first dielectric layers, the first height correction layer having a first height that is determined based on a first pattern density of the first region; depositing a conductive material on the substrate to fill one or more first trenches surrounded by the first dielectric layers and the first height correction layer and cover the first dielectric layers and the first height correction layer; and performing a planarization process to planarize the conductive material and the first height correction layer until uncovering the first dielectric layers.

2 . The method of claim 1 , further comprising:
forming a second height correction layer on a second one of the first dielectric layers, the second one of the first dielectric layers being closer than the first one of the first dielectric layers to a center of the first region and having a second height that is greater than the first height of the first one of the first dielectric layers.

3 . The method of claim 1 , further comprising:
forming the dielectric material on the substrate within a second region to form one or more second dielectric layers that are spaced from one another; depositing the conductive material on the substrate to fill one or more second trenches surrounded by the second dielectric layers and cover the second dielectric layers; and performing the planarization process to planarize the conductive material until uncovering the second dielectric layers, wherein the first pattern density is greater than a second pattern density of the second region.

4 . The method of claim 3 , further comprising:
forming a second height correction layer on one of the second dielectric layers, the second height correction layer having a second height that is determined based on the second pattern density of the second region, the second height being less than the first height, wherein depositing the conductive material on the substrate to fill the second trenches surrounded by the second dielectric layers and cover the second dielectric layers includes depositing the conductive material on the substrate to fill the second trenches surrounded by the second dielectric layers and the second height correction layer and cover the second dielectric layers and the second height correction layer, and performing the planarization process to planarize the conductive material until uncovering the second dielectric layers includes performing the planarization process to planarize the conductive material and the second height correction layer until uncovering the second dielectric layers.

5 . The method of claim 1 , wherein the planarization process is a chemical mechanical polishing (CMP) process.

6 . The method of claim 1 , wherein the dielectric material is formed on the substrate in a chemical vapor deposition (CVD) process.

7 . The method of claim 1 , wherein the conductive material includes ruthenium (Ru).

8 . The method of claim 1 , wherein the conductive material includes copper (Cu).

9 . The method of claim 1 , wherein the conductive material includes tungsten (W).

10 . The method of claim 1 , wherein the dielectric material is formed on the substrate in a spin-on film deposition process.

11 . A wafer processing system, comprising:
a film formation module configured to form a conductive material, a dielectric material and a first height correction layer; a planarization module configured to perform a planarization process to planarize the conductive material and the first height correction layer; and a controller coupled to the film formation module and the planarization module, the controller configured to control
the film formation module to form the dielectric material on a substrate within a first region to form one or more first dielectric layers that are spaced from one another, to form the first height correction layer on a first one of the first dielectric layers, the first height correction layer having a first height that is determined based on a first pattern density of the first region, and to form the conductive material on the substrate to fill one or more first trenches surrounded by the first dielectric layers and the first height correction layer and cover the first dielectric layers and the first height correction layer, and
the planarization module to perform the planarization process to planarize the conductive material and the first height correction layer until uncovering the first dielectric layers.

12 . The wafer processing system of claim 11 , wherein
the film formation module is further configured to form a second height correction layer, and the controller is further configured to control the film formation module to form the second height correction layer on a second one of the first dielectric layers, the second one of the first dielectric layers being closer than the first one of the first dielectric layers to a center of the first region and having a second height that is greater than the first height of the first one of the first dielectric layers.

13 . The wafer processing system of claim 11 , wherein the controller is further configured to control
the film formation module to form the dielectric material on the substrate within a second region to form one or more second dielectric layers that are spaced from one another, and to form the conductive material on the substrate to fill one or more second trenches surrounded by the second dielectric layers and cover the second dielectric layers, and the planarization module to perform the planarization process to planarize the conductive material until uncovering the second dielectric layers, wherein the first pattern density is greater than a second pattern density of the second region.

14 . The wafer processing system of claim 13 , wherein
the film formation module is further configured to form a second height correction layer, and the controller is further configured to control
the film formation module to form the second height correction layer on one of the second dielectric layers, the second height correction layer having a second height that is determined based on the second pattern density of the second region, the second height being less than the first height, and to form the conductive material on the substrate to fill the second trenches surrounded by the second dielectric layers and the second height correction layer and cover the second dielectric layers and the second height correction layer, and
the planarization module to perform the planarization process to planarize the conductive material and the second height correction layer until uncovering the second dielectric layers.

15 . The wafer processing system of claim 11 , wherein the planarization process is a chemical mechanical polishing (CMP) process.

16 . The wafer processing system of claim 11 , wherein the dielectric material is formed on the substrate in a chemical vapor deposition (CVD) process.

17 . The wafer processing system of claim 11 , wherein the conductive material includes ruthenium (Ru).

18 . The wafer processing system of claim 11 , wherein the conductive material includes copper (Cu).

19 . The wafer processing system of claim 11 , wherein the conductive material includes tungsten (W).

20 .

Assignees

• Tokyo Electron Ltd

Inventors

• Grzeskowiak Jodi
• Power David
• Conklin David

Classifications

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H10P72/0472

  comprising at least one polishing chamber · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title