Dopants to Decrease BiSbX's and YBiPt's Bandgap for Optimal Current-In-Plane (CIP) Conductivity

US2025228140A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025228140-A1
Application numberUS-202519011136-A
CountryUS
Kind codeA1
Filing dateJan 6, 2025
Priority dateJan 10, 2024
Publication dateJul 10, 2025
Grant date

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Abstract

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The present disclosure generally relates to topological semi-metal (TSM) and topological insulator (TI) based spin-orbit torque (SOT) devices and a method of forming thereof. TI or TSM-based SOT device (such as that with BiSb in the SOT layer) has been proposed for applications in magnetic switching and sensor applications, where current flows in a CIP (current-in-plane) or CPP (current-perpendicular-to-the-plane) direction, respectively. For CPP SOT devices, the requirement for the TI or TSM layer's bulk property is to be more insulating, to minimize shunting. However, for CIP SOT devices, the requirement for the TI or TSM layer's bulk property is to be more conductive, for less power consumption. Disclosed herein are various embodiments covering types and amounts of dopants for the TI or TSM layer, to decrease the bandgap of the TI or TSM layer for CIP SOT devices, thereby increasing the bulk conductivity for lower power consumption.

First claim

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What is claimed is: 1 . A current-in-plane (CIP) spin orbit torque (SOT) device, comprising: a buffer layer; a doped bismuth antimony (BiSb) layer over the buffer layer, the doped BiSb layer comprising BiSb and a Ge—TiO, Ge-VO, or X-N dopant for controlling a bandgap of the BiSb layer, wherein the X-N dopant comprises N and X is one or more elements selected from the group consisting of: Sc, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W, Cu, Rh, Ir, Pd, Pt, B, Al, Ga, In, Si, Ge, Sn, As, S, Se, Te, and alloy combinations thereof; an interlayer over the BiSb layer; and a ferromagnetic layer over the interlayer. 2 . The CIP SOT device of claim 1 , wherein the amount of dopant between 0.1 at. % to about 8 at. %, and wherein a thickness of the doped BiSb layer is between about 50 Å to about 600 Å. 3 . The CIP SOT device of claim 1 , wherein one or more of the buffer layer, the interlayer, and the ferromagnetic layer is also doped with the dopant. 4 . The CIP SOT device of claim 1 , wherein the doped BiSb layer has an amount of conductivity of about 1.5×10 5 ohm −1 m −1 or above. 5 . The CIP SOT device of claim 1 , wherein the doped BiSb layer comprises BiSb and the X-N dopant, wherein the X-N dopant comprises N and X is selected from the group consisting of: Sc, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W, and alloy combinations thereof. 6 . The CIP SOT device of claim 1 , wherein the doped BiSb layer comprises BiSb and the X-N dopant, wherein the X-N dopant comprises N and X is selected from the group consisting of: Cu, Pd, Al, Si, Ge, and alloy combinations thereof. 7 . A magnetic recording device comprising the CIP SOT device of claim 1 . 8 . A magnetoresistive random access memory device comprising the CIP SOT device of claim 1 . 9 . A logic device comprising the CIP SOT device of claim 1 . 10 . A current-in-plane (CIP) spin orbit torque (SOT) device, comprising: a buffer layer; a doped yttrium bismuth platinum (YBiPt) layer over the buffer layer, the doped YBiPt layer comprising YBiPt and a X-N dopant, a X-C dopant, or a X-O dopant, where X is one or more elements selected from the group consisting of: Sc, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W, Cu, Rh, Ir, Pd, Pt, B, Al, Ga, In, Si, Ge, Sn, As, S, Se, Te, Ge—Ti, and alloy combinations thereof; an interlayer over the YBiPt layer; and a ferromagnetic layer over the interlayer. 11 . The CIP SOT device of claim 10 , wherein the amount of C dopant between 0.1 at. % to about 8 at. %, and wherein a thickness of the doped YBiPt layer is between about 50 Å to about 600 Å. 12 . The CIP SOT device of claim 10 , wherein one or more of the buffer layer, the interlayer, and the ferromagnetic layer is also doped with the X-N dopant, the X-C dopant, or the X-O dopant. 13 . A magnetic recording device comprising the CIP SOT device of claim 10 . 14 . A magnetoresistive random access memory device comprising the CIP SOT device of claim 10 . 15 . A logic device comprising the CIP SOT device of claim 10 . 16 . A current-in-plane (CIP) spin orbit torque (SOT) device, comprising: a buffer layer; a doped bismuth antimony (BiSb) layer over the buffer layer, the doped BiSb layer comprising BiSb and a dopant for controlling a bandgap of the BiSb layer, wherein the dopant is one or more of elements selected from the group consisting of: B, Al, Ga, In, N, C, Si, Ge, Sn, P, As, Ni, Cu, Zn, Mg, Zr, Nb, Mo, Ta, Hf, W, Pt, Ir, Ge—TiO, GeN, GeWN, Ge-VO, and alloy dopant combinations thereof; an interlayer over the BiSb layer; and a ferromagnetic layer over the interlayer. 17 . The CIP SOT device of claim 16 , wherein the amount of dopant between 0.1 at. % to about 8 at. %, and wherein a thickness of the doped BiSb layer is between about 50 Å to about 600 Å. 18 . The CIP SOT device of claim 16 , wherein one or more of the buffer layer, the interlayer, and the ferromagnetic layer is also doped with the dopant. 19 . The CIP SOT device of claim 16 , wherein the doped BiSb layer has an amount of conductivity of about 1.5×10 5 ohm −1 m −1 or above. 20 . A magnetic recording device comprising the CIP SOT device of claim 16 . 21 . A magnetoresistive random access memory device comprising the CIP SOT device of claim 16 . 22 . A logic device comprising the CIP SOT device of claim 16 .

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Classifications

  • using Hall-effect devices · CPC title

  • Magnetoresistive devices · CPC title

  • H10N50/85Primary

    Materials of the active region · CPC title

  • details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

  • using galvano-magnetic devices, e.g. Hall-effect devices · CPC title

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What does patent US2025228140A1 cover?
The present disclosure generally relates to topological semi-metal (TSM) and topological insulator (TI) based spin-orbit torque (SOT) devices and a method of forming thereof. TI or TSM-based SOT device (such as that with BiSb in the SOT layer) has been proposed for applications in magnetic switching and sensor applications, where current flows in a CIP (current-in-plane) or CPP (current-perpend…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification H10N50/85. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jul 10 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).