Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025212400-A1
Application number	US-202519077107-A
Country	US
Kind code	A1
Filing date	Mar 12, 2025
Priority date	Jun 8, 2020
Publication date	Jun 26, 2025
Grant date	—

Abstract

A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a preliminary stack structure including sacrificial layers and interlayer insulating layers alternately stacked in a vertical direction; forming channel structures penetrating through the preliminary stack structure; forming a first trench, a second trench, and a third trench penetrating through the preliminary stack structure and spaced apart from each other,
wherein the first trench includes:
a first line portion extending in a first direction perpendicular to the vertical direction; and
second line portions extending from the first line portion in a second direction away from the second trench,

wherein the second trench includes:
a third line portion extending in the first direction; and
fourth line portions extending from the third line portion in a third direction away from the first trench,

wherein the second line portions are spaced apart from each other in the first direction,
wherein the fourth line portions are spaced apart from each other in the first direction, and
wherein the third trench is between the first line portion and the third line portion and extends in the first direction;
forming openings by etching the sacrificial layers exposed by the first, second, and third trenches; and forming conductive layers within the openings, wherein a length of the third trench in the first direction is greater than a distance between the second line portions adjacent to each other in the first direction.

2 . The method of claim 1 , wherein the conductive layers include:
first conductive layers between the second line portions; second conductive layers between the fourth line portions; and third conductive layers between the first line portion and the second line portion.

3 . The method of claim 2 , wherein an uppermost third conductive layer of the third conductive layers is at the same level as an uppermost first conductive layer of the first conductive layers and an uppermost second conductive layer of the second conductive layers.

4 . The method of claim 1 , wherein the channel structures include:
first channel structures between the second line portions; and second channel structures between the fourth line portions.

5 . The method of claim 1 , further comprising
forming separation structures after forming the conductive layers; and forming bit lines connected to the channel structures after forming the separation structures.

6 . The method of claim 5 , wherein the separation structures include:
a first separation structure within the first trench; a second separation structure within the second trench; and a third separation structure within the third trench.

7 . The method of claim 5 , wherein the bit lines do not overlap with the third trench in the vertical direction.

8 . The method of claim 5 , further comprising:
forming dummy channel structures penetrating through the preliminary stack structure, before forming the first trench, the second trench, and the third trench, wherein the dummy channel structures are not connected to the bit lines, and wherein the dummy channel structures include:
first dummy channel structures between the first line portion and the third trench; and
second dummy channel structures between the third line portion and the third trench.

9 . The method of claim 1 , further comprising:
forming a peripheral circuit region including circuit devices; and forming a first substrate and a lower separation region, wherein the preliminary stack structure is formed on the first substrate and the lower separation region.

10 . The method of claim 9 , wherein first substrate includes a first portion and a second portion spaced apart from the first portion,
wherein the first portion is a first polysilicon plate portion, wherein the second portion is a second polysilicon plate portion, and wherein the lower separation region includes an insulating material between the first portion and the second portion.

11 . The method of claim 10 , wherein the first trench is on the first portion, and wherein the second trench is on the second portion.

12 . The method of claim 10 , wherein the first substrate further includes a third portion between the first portion and the second portion, and
wherein the third portion is spaced apart from the first portion and the second portion.

13 . The method of claim 12 , wherein the third trench is on the third portion.

14 . A method of manufacturing a semiconductor device, comprising:
forming a peripheral circuit region including circuit devices; and forming a first substrate and a lower separation region on the peripheral circuit region,
wherein first substrate includes a first polysilicon portion, a second polysilicon portion, and a third polysilicon portion between the first polysilicon portion and the second polysilicon portion, and
wherein the lower separation region includes an insulating material between the first polysilicon portion and the third polysilicon portion, and between the third polysilicon portion and the second polysilicon portion;
forming a preliminary stack structure on the first substrate and the lower separation region and including sacrificial layers and interlayer insulating layers alternately stacked in a vertical direction; forming channel structures penetrating through the preliminary stack structure; forming trenches penetrating through the preliminary stack structure and spaced apart from each other,
wherein the trenches include a first trench on the first polysilicon portion and a second trench on the second polysilicon portion,
wherein the first trench includes:
a first line portion extending in a first direction perpendicular to the vertical direction; and
second line portions extending from the first line portion in a second direction away from the second trench,

wherein the second trench includes:
a third line portion extending in the first direction; and
fourth line portions extending from the third line portion in a third direction away from the first trench,

wherein the second line portions are spaced apart from each other in the first direction, and
wherein the fourth line portions are spaced apart from each other in the first direction;
forming openings by etching the sacrificial layers exposed by the first and second trenches; and forming conductive layers within the openings.

15 . The method of claim 14 , wherein the conductive layers include:
first conductive layers between the second line portions; second conductive layers between the fourth line portions; and third conductive layers between the first line portion and the second line portion, and wherein an uppermost third conductive layer of the third conductive layers is at the same level as an uppermost first conductive layer of the first conductive layers and an uppermost second conductive layer of the second conductive layers.

16 . The method of claim 14 , further comprising
forming separation structures after forming the conductive layers; and forming bit lines connected to the channel structures after forming the separation structures, wherein the separation structures include:
a first separation structure within the first trench;
a second separation structure within the second trench; and
a third separation structure within the third trench, and
wherein the bit lines do not overlap with the third trench in the vertical direction.

17 . A method of manufacturing a semiconductor dev

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jo Sangyoun
• Kanamori Kohji
• Jung Kwangyoung
• Han Jeehoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title