Packaged electronic devices having dielectric substrates with thermally conductive adhesive layers

Patent metadata

Field	Value
Publication number	US-2025149432-A1
Application number	US-202519013061-A
Country	US
Kind code	A1
Filing date	Jan 8, 2025
Priority date	Jan 27, 2021
Publication date	May 8, 2025
Grant date	—

Abstract

A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer

First claim

That which is claimed is:

1 . A packaged electronic device, comprising:
a power semiconductor die that comprises a first terminal and a second terminal; a lead frame comprising a lower side and an upper side that comprises a die pad region; a first lead and a second lead; a dielectric substrate; a lower metal cladding layer on a lower side of the dielectric substrate; a lower metal braze layer in between the lower metal cladding layer and the dielectric substrate; an upper metal cladding layer on an upper side of the dielectric substrate; an upper metal braze layer in between the dielectric substrate and the upper metal cladding layer; and a substrate attach material that comprises a solder or sintering material in between the upper metal cladding layer and the lead frame, wherein the power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the substrate attach material.

2 . The packaged electronic device of claim 1 , wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame.

3 . The packaged electronic device of claim 2 , wherein the upper metal braze layer is directly attached to the ceramic substrate and to the lower side of the upper metal cladding layer.

4 . The packaged electronic device of claim 3 , wherein the lower metal braze layer is directly attached to the ceramic substrate and to the upper side of the lower metal cladding layer.

5 . The packaged electronic device of claim 4 , further comprising an overmold package that encapsulates an upper side and side surfaces of the power semiconductor die.

6 . The packaged electronic device of claim 5 , wherein the dielectric substrate comprises a ceramic substrate.

7 . The packaged electronic device of claim 1 , wherein the lead frame and the lower metal cladding layer are formed of the same metal.

8 . The packaged electronic device of claim 1 , wherein the power semiconductor die is soldered to the leadframe using a die attach material.

9 . The packaged electronic device of claim 1 , wherein the upper metal cladding layer comprises a plated metal layer.

10 . A packaged electronic device, comprising:
a first power semiconductor die that comprises a first terminal and a second terminal; a second power semiconductor die that comprises a third terminal and a fourth terminal; a lead frame comprising a lower side and an upper side; a first lead, a second lead, a third lead and a fourth lead; a dielectric substrate; a lower metal cladding layer on a lower side of the dielectric substrate; a lower metal braze layer in between the lower metal cladding layer and the dielectric substrate; an upper metal cladding layer on an upper side of the dielectric substrate; an upper metal braze layer in between the dielectric substrate and the upper metal cladding layer; and a substrate attach material in between the upper metal cladding layer and the lead frame, wherein the first power semiconductor die and the second power semiconductor die are mounted on the lead frame and the lead frame is on an upper side of the substrate attach material.

11 . The packaged electronic device of claim 10 , wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame.

12 . The packaged electronic device of claim 11 , wherein the upper metal braze layer is directly attached to the ceramic substrate and to the lower side of the upper metal cladding layer and the lower metal braze layer is directly attached to the ceramic substrate and to the upper side of the lower metal cladding layer.

13 . The packaged electronic device of claim 12 , further comprising an overmold package that encapsulates an upper side and side surfaces of the power semiconductor die.

14 . The packaged electronic device of claim 13 , wherein the lead frame and the lower metal cladding layer are formed of the same metal.

15 . The packaged electronic device of claim 14 , wherein the upper metal cladding layer comprises a plated metal layer.

16 . A packaged electronic device, comprising:
a first power semiconductor die that comprises a first terminal and a second terminal; a second power semiconductor die that comprises a third terminal and a fourth terminal; a lead frame comprising a lower side and an upper side; a first lead, a second lead, a third lead and a fourth lead; a dielectric substrate; a lower metal cladding layer on a lower side of the dielectric substrate; a lower metal braze layer in between the lower metal cladding layer and the dielectric substrate; an upper metal cladding layer on an upper side of the dielectric substrate; an upper metal braze layer in between the dielectric substrate and the upper metal cladding layer; and a thermally conductive adhesive paste in between the upper metal cladding layer and the lead frame, wherein the first power semiconductor die and the second power semiconductor die are mounted on the lead frame and the lead frame is on an upper side of the substrate attach material.

17 . The packaged electronic device of claim 16 , wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame.

18 . The packaged electronic device of claim 16 , further comprising an overmold package that encapsulates an upper side and side surfaces of the power semiconductor die.

19 . The packaged electronic device of claim 16 , wherein the lead frame and the lower metal cladding layer are formed of the same metal.

20 . The packaged electronic device of claim 16 , wherein the upper metal cladding layer comprises a plated metal layer.

Assignees

• Wolfspeed Inc

Inventors

• Seal Sayan
• Saxena Kuldeep
• Balaraman Devarajan

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title