Methods and apparatus for synchronizing communication with a memory controller
US-9466353-B2 · Oct 11, 2016 · US
using several loops, e.g. for redundant clock signal generation
using several loops, e.g. for redundant clock signal generation · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H03L7/07 |
| Official title | using several loops, e.g. for redundant clock signal generation |
| Display label | using several loops, e.g. for redundant clock signal generation |
| Total patents | 665 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 56 |
| 2016 | 68 |
| 2017 | 39 |
| 2018 | 46 |
| 2019 | 74 |
| 2020 | 98 |
| 2021 | 94 |
| 2022 | 68 |
| 2023 | 50 |
| 2024 | 31 |
| 2025 | 36 |
| 2026 | 5 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor device
US-9413525-B2 · Aug 9, 2016 · US
Systems and methods for configuring a semiconductor device
US-9350360-B2 · May 24, 2016 · US
Semiconductor device
US-9236869-B2 · Jan 12, 2016 · US
Semiconductor device
US-2015381344-A1 · Dec 31, 2015 · US
Low-noise flexible frequency clock generation from two fixed-frequency references
US-9225508-B1 · Dec 29, 2015 · US
Distributed clock synchronization
US-2015364170-A1 · Dec 17, 2015 · US
Afll with increased timing margin
US-2015365093-A1 · Dec 17, 2015 · US
Low-noise flexible frequency clock generation from two fixed-frequency references
US-9215062-B1 · Dec 15, 2015 · US
Phase interpolator
US-9208130-B1 · Dec 8, 2015 · US
Receiving circuit
US-2015349783-A1 · Dec 3, 2015 · US
Methods and apparatus for performing bit swapping in clock data recovery circuitry
US-9203604-B1 · Dec 1, 2015 · US
Electronic circuit, radar apparatus, and method of performing self-diagnosis on radar apparatus
US-9197223-B2 · Nov 24, 2015 · US
Clock skew management systems, methods, and related components
US-2015323959-A1 · Nov 12, 2015 · US
Clock skew management systems, methods, and related components
US-2015323958-A1 · Nov 12, 2015 · US
Apparatus and methods for clock and data recovery
US-9184909-B1 · Nov 10, 2015 · US
Clock and Data Recovery Using Receiver Clock Spread Spectrum Modulation and Offset Compensation
US-2015312019-A1 · Oct 29, 2015 · US
Circuit and method for clock and data recovery
US-2015304097-A1 · Oct 22, 2015 · US
Low-power and all-digital phase interpolator-based clock and data recovery architecture
US-9166605-B2 · Oct 20, 2015 · US
Methods and apparatus for synchronizing communication with a memory controller
US-9159388-B2 · Oct 13, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H03L7/07?
- CPC H03L7/07 is the Cooperative Patent Classification code for “using several loops, e.g. for redundant clock signal generation.”
- How many patents are filed under CPC H03L7/07 (using several loops, e.g. for redundant clock signal generation)?
- Our database includes 665 publications tagged with this CPC code.
- Is patent activity under CPC H03L7/07 growing?
- Publication counts under this code: 31 in 2024 vs 36 in 2025 (latest complete years).