Semiconductor packages and method of forming the same

Patent metadata

Field	Value
Publication number	US-2025087627-A1
Application number	US-202418959684-A
Country	US
Kind code	A1
Filing date	Nov 26, 2024
Priority date	Mar 31, 2021
Publication date	Mar 13, 2025
Grant date	—

Abstract

A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a first integrated circuit structure, comprising:
a logic die, comprising a first substrate, a first through substrate via, and a first bonding layer disposed on a back side of the first substrate; and
a plurality of memory dies stacked on the front side of the logic die; and
a second integrated circuit structure, comprising a second substrate, a second through substrate via, and a second bonding layer disposed on a back side of the second substrate,
wherein the first integrated circuit structure is bonded to the second integrated circuit structure through the first bonding layer and the second bonding layer and through the first through substrate via and the second through substrate via, wherein a metal portion ( 615 ) containing a nitrogen atom content is disposed between the first through substrate via and the second through substrate via.

2 . The semiconductor package of claim 1 , wherein the first bonding layer of the first integrated circuit structure has a gradient nitrogen concentration.

3 . The semiconductor package of claim 2 , wherein the nitrogen concentration of the first bonding layer of the first integrated circuit structure is increased towards the second bonding layer of the second integrated circuit structure.

4 . The semiconductor package of claim 1 , wherein the first bonding layer has a first surface bonding to the second bonding layer and a second surface opposite to the first surface, and the second surface is rough and uneven.

5 . The semiconductor package of claim 1 , wherein a width of the logic die is greater than a width of the memory dies.

6 . The semiconductor package of claim 1 , wherein the metal portion comprises metal nitride or metal oxynitride.

7 . The semiconductor package of claim 1 , further comprising a dielectric encapsulation surrounding the second integrated circuit structure and in contact with the first bonding layer.

8 . A semiconductor package, comprising:
a first die, comprising a first substrate, a first metal feature in the first substrate, and a first bonding layer disposed on a back side of the first substrate and around the first metal feature, wherein a non-metal element of the first bonding layer is included in the first metal feature; and a second die, comprising a second substrate, a second metal feature in the second substrate, and a second bonding layer disposed on a back side of the second substrate around the metal feature, wherein the first bonding layer is connected to the second bonding layer, and the first metal feature is bonded to the second metal feature.

9 . The semiconductor package of claim 8 , wherein the non-metal material of the first bonding layer comprises nitrogen, oxygen or a combination thereof.

10 . The semiconductor package of claim 8 , wherein the first metal feature comprises a lower portion and an upper portion, and the upper includes the non-metal element of the first bonding layer.

11 . The semiconductor package of claim 10 , wherein a thickness of the upper portion is less than a thickness of the first bonding layer.

12 . The semiconductor package of claim 10 , wherein an interface between the upper portion and the upper portion is rough and uneven.

13 . The semiconductor package of claim 8 , wherein the first bonding layer has a first surface bonding to the second bonding layer and a second surface opposite to the first surface, and the second surface is rough and uneven.

14 . The semiconductor package of claim 8 , wherein a width of the first metal feature is less than a width of the second metal feature.

15 . A semiconductor package, comprising:
a first die, comprising:
a first silicon substrate;
a first bonding metal feature disposed in the first silicon substrate;
a first insulating liner disposed between the first bonding metal feature and the first silicon substrate; and
a first bonding layer having a gradient nitrogen concentration and laterally extending from the first insulating liner,
wherein a top surface of the first bonding metal feature is flush with a top surface of the first bonding layer.

16 . The semiconductor package of claim 15 , further comprising:
a second die, comprising:
a second silicon substrate;
a second bonding metal feature disposed in the second silicon substrate;
a second insulating liner disposed between the second bonding metal feature and the second silicon substrate; and
a second bonding layer laterally extending from the second insulating liner,
wherein the first bonding layer is connected to the second bonding layer, and the first bonding metal feature is bonded to the second bonding metal feature.

17 . The semiconductor package of claim 16 , wherein a width of the first bonding metal feature is less than a width of the second bonding metal feature.

18 . The semiconductor package of claim 16 , wherein the second insulating liner is in contact with the first bonding layer.

19 . The semiconductor package of claim 16 , wherein the second bonding layer and the first bonding layer comprises different materials.

20 . The semiconductor package of claim 15 , wherein the first bonding metal feature comprises a nitridized metal portion and an underlying metal portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Hung-Jui
• Tsai Hui-Jung
• Wang Chia-Wei
• Chang Yu-Tzu

Classifications

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title