System on chip

Patent metadata

Field	Value
Publication number	US-2025068579-A1
Application number	US-202418640848-A
Country	US
Kind code	A1
Filing date	Apr 19, 2024
Priority date	Aug 25, 2023
Publication date	Feb 27, 2025
Grant date	—

Abstract

A system on chip is provided. The system on chip includes a bus including a data channel through which data is transmitted in at least one direction and a master interface configured to receive first data from the data channel, perform a bit operation on the first data and on second data input before input of the first data, determine an encoding operation for the first data based on a result of the bit operation, perform the encoding operation on the first data, to obtain encoded data, and provide the encoded data and a transformation signal indicating the encoding operation to the data channel.

First claim

What is claimed is:

1 . A system on chip comprising:
a bus including a data channel through which data is transmitted in at least one direction; and a master interface configured to
receive first data from the data channel,
perform a bit operation on the first data and on second data input before input of the first data,
determine an encoding operation for the first data based on a result of the bit operation;
perform the encoding operation on the first data, to obtain encoded data; and
provide the encoded data and a transformation signal indicating the encoding operation to the data channel.

2 . The system on chip of claim 1 , wherein the encoding operation comprises a maintenance operation, an invert operation, or a circular shift operation.

3 . The system on chip of claim 2 , wherein the transformation signal is 1 bit.

4 . The system on chip of claim 3 , wherein the master interface is configured to provide a first transformation signal indicating the invert operation, and a second transformation signal indicating the circular shift operation, and
wherein the first transformation signal and the second transformation signal are the same.

5 . The system on chip of claim 3 , wherein the master interface is configured to provide a first transformation signal indicating the invert operation, and a second transformation signal indicating the maintenance operation, and
wherein the first transformation signal and the second transformation signal are different from each other.

6 . The system on chip of claim 2 , wherein the circular shift operation includes shifting the first data by 2 bit units.

7 . The system on chip of claim 1 , wherein the master interface comprises:
a first bit operator that outputs an XOR result value by performing an XOR bit operation on the first data and the second data; and a second bit operator that outputs an XNOR result value by performing an XNOR bit operation on (i) first shift data obtained by performing a circular shift operation on the first data, and (ii) the second data.

8 . The system on chip of claim 7 , wherein the master interface comprises:
a first adder configured to output a first sum value by bit counting the XOR result value; a second adder configured to output a second sum value by bit counting the XNOR result value; a first comparator configured to output an invert signal based on the first sum value and a number of bits of the first data; and a second comparator configured to output a shift signal based on the first sum value, the second sum value, and the number of bits of the first data.

9 . The system on chip of claim 8 , wherein the first comparator is configured to output the invert signal based on whether the first sum value is greater than the number of bits of the first data divided by two.

10 . The system on chip of claim 8 , wherein the second comparator is configured to output the shift signal based on whether the second sum value is greater than a difference between the number of bits of the first data and the first sum value.

11 . The system on chip of claim 1 , wherein the master interface comprises a control unit configured to receive an invert signal, a shift signal, and at least a part of the first data,
wherein the invert signal and the shift signal are based on a result of the bit operation.

12 . The system on chip of claim 11 , wherein the control unit is configured to output an invert enable signal for the invert signal and a shift enable signal for the shift signal, and
wherein the master interface is configured to
receive the invert signal, the shift signal, the invert enable signal, and the shift enable signal,
enable the invert signal and the shift signal, and
output the transformation signal.

13 . The system on chip of claim 12 , wherein the control unit is configured to turn off the invert enable signal and the shift enable signal when the first data and the second data are not provided to the data channel in a burst mode.

14 . A system on chip comprising:
a bus including a data channel through which data is transmitted in at least one direction; and a slave interface configured to
receive, from the data channel, encoded data and a transformation signal indicating an encoding operation performed to obtain the encoded data, and
performs a maintenance operation, an invert operation, or a circular shift operation on the encoded data based on at least a part of the encoded data and based on the transformation signal.

15 . The system on chip of claim 14 , wherein the slave interface is configured to perform the invert operation or the circular shift operation based on the transformation signal being 1 bit and at a turn-on level.

16 . The system on chip of claim 15 , wherein the slave interface is configured to perform the invert operation based on the transformation signal being at the turn-on level and based on a first bit of the encoded data and a second bit of the encoded data, adjacent to one another, being equal.

17 . The system on chip of claim 15 , wherein the slave interface is configured to perform the circular shift operation based on the transformation signal being at the turn-on level and based on a first bit of the encoded data and a second bit of the encoded data, adjacent to one another, being different.

18 . A system on chip comprising:
a master interface configured to
perform a bit operation on first data and second data input before input of the first data,
perform an encoding operation on the first data based on a result of the bit operation, to obtain encoded data, and
output the encoded data and a transformation signal indicating the encoding operation;
a bus including
a data flipflop configured to latch the encoded data based on a clock signal, a clock gating circuit configured to clock-gate the clock signal, and a data channel configured to transmit the encoded data in at least one direction through the data flipflop; and
a slave interface configured to
receive the encoded data and the transformation signal from the bus, and
performs a decoding operation on the encoded data based on at least a part of the encoded data and based on the transformation signal.

19 . The system on chip of claim 18 , wherein:
the encoding operation is a first maintenance operation and the decoding operation is a second maintenance operation, the encoding operation is a first invert operation and the decoding operation is a second invert operation, or the encoding operation is a first circular shift operation and the decoding operation is a second circular shift operation.

20 . The system on chip of claim 19 , wherein the encoding operation is the first circular shift operation and the decoding operation is the second circular shift operation, and
wherein a shift direction in the encoding operation and a shift direction in the decoding operation are different from one another.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Minha

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title

• G06F2115/02

  System on chip [SoC] design · CPC title

• G06F2117/04

  Clock gating · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title