Data inversion circuit

Patent metadata

Field	Value
Publication number	US-10545888-B2
Application number	US-201715493666-A
Country	US
Kind code	B2
Filing date	Apr 21, 2017
Priority date	Nov 21, 2016
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

A data inversion circuit in accordance with an embodiment may include a data input circuit and an inversion latch circuit. The data input circuit may output latch data by latching input data, perform a data inversion by performing a logical operation on the latch data and flag data, generate selective inversion data, and output data composed of multiple bits by aligning the selective inversion data. The inversion latch circuit may generate the flag data by latching inversion data.

First claim

What is claimed is:

1. A data inversion circuit comprising:
a data input circuit configured to output latch data by latching input data, perform a data inversion by performing a logical operation on the latch data and flag data, generate selective inversion data, and output data composed of multiple bits by aligning the selective inversion data; and
an inversion latch circuit configured to generate the flag data by latching inversion data,
wherein the data input circuit includes;
a first data bus inversion controller configured to output a first selective inversion data by performing a logical operation on a first latch data and a first flag data; and
a second data bus inversion controller configured to output a second selective inversion data by performing a logical operation on a second latch data and a second flag data.

2. The data inversion circuit according to claim 1 , wherein the data inversion circuit includes a plurality of data input circuits, the inversion latch circuit is shared by the plurality of data input circuits.

3. The data inversion circuit according to claim 1 , wherein the data input circuit includes:
a latch circuit configured to latch the input data in response to a data strobe signal, and output first latch data and second latch data;
a data bus inversion circuit configured to output first selective inversion data by performing a logical operation on the first latch data and first flag data, and output second selective inversion data by performing a logical operation on the second latch data and second flag data;
an alignment circuit configured to align the first selective inversion data and the second selective inversion data in synchronization with the data strobe signal, and output the aligned data in response to a strobe signal; and
a drive circuit configured to drive the aligned data in synchronization with an enable signal, and output data composed of multiple bits.

4. The data inversion circuit according to claim 3 , wherein:
the first latch data is synchronized with a rising edge of the data strobe signal; and
the second latch data is synchronized with a rising edge of an inversion signal of the data strobe signal.

5. The data inversion circuit according to claim 3 , wherein:
the first flag data is synchronized with a rising edge of the data strobe signal; and
the second flag data is synchronized with a rising edge of an inversion signal of the data strobe signal.

6. The data inversion circuit according to claim 3 , wherein:
the data bus inversion circuit outputs a logic-high signal when two input data signals have the same logic level; and
the data bus inversion circuit outputs a logic-low signal when two input data signals have different logic levels.

7. The data inversion circuit according to claim 3 , wherein the data bus inversion circuit includes a logic gate configured to perform an exclusive NOR operation on two input data signals.

8. The data inversion circuit according to claim 7 , wherein the alignment circuit includes:
a first flip-flop configured to hold the first selective inversion data in synchronization with the data strobe signal, and output first alignment data;
a delay circuit configured to output second alignment data by delaying the second selective inversion data;
a second flip-flop configured to hold the first alignment data in synchronization with the data strobe signal, and output third alignment data;
a third flip-flop configured to hold the second alignment data in synchronization with the data strobe signal, and output fourth alignment data;
a first data output circuit configured to latch the first to fourth alignment data, and output data of a first group in synchronization with a first strobe signal; and
a second data output circuit configured to latch the first to fourth alignment data, and output data of a second group in synchronization with a second strobe signal.

9. The data inversion circuit according to claim 8 , wherein the first alignment data and the second alignment data are output based on a first rising edge of the data strobe signal.

10. The data inversion circuit according to claim 8 , wherein the third alignment data and the fourth alignment data are output based on a second rising edge of the data strobe signal.

11. The data inversion circuit according to claim 8 , wherein the second strobe signal is activated later than the first strobe signal by a predetermined time period.

12. The data inversion circuit according to claim 8 , wherein the enable signal is activated later than the second strobe signal by a predetermined time period.

13. A data inversion circuit comprising:
a latch circuit configured to output first latch data by latching input data in response to a first data strobe signal, latch the input data in response to a second data strobe signal, which is an inversion signal of the first data strobe signal, and output second latch data;
a first data bus inversion controller configured to output the first selective inversion data by performing a logical operation on the first latch data and the first flag data;
a second data bus inversion controller configured to output the second selective inversion data by performing a logical operation on the second latch data and the second flag data;
an alignment circuit configured to align the first selective inversion data by synchronizing with the first data strobe signal, align the second selective inversion data in synchronization with the second data strobe signal, and output aligned data in response to a strobe signal; and
a drive circuit configured to drive the aligned data in synchronization with an enable signal, and output data composed of multiple bits.

14. The data inversion circuit according to claim 13 , further comprising an inversion latch circuit configured to generate the first flag data by latching inversion data in response to the first data strobe signal, and generate the second flag data by latching the inversion data in response to the second data strobe signal.

15. The data inversion circuit according to claim 13 , wherein:
the first latch data and the first flag data are synchronized with a rising edge of the first data strobe signal; and
the second latch data and the second flag data are synchronized with a rising edge of the second data strobe signal.

16. The data inversion circuit according to claim 13 , wherein each of the first data bus inversion controller and the second data bus inversion controller includes a logic gate configured to perform an exclusive NOR operation on two input data.

17. The data inversion circuit according to claim 13 , wherein the alignment circuit includes:
a first flip-flop configured to hold the first selective inversion data in synchronization with the second data strobe signal, and output first alignment data;
a delay circuit configured to output second alignment data by delaying the second selective inversion data;
a second flip-flop configured to hold the first alignment data in synchronization with the second data strobe signal, and output third alignment data;
a third flip-flop configured to hold the second alignment data in synchronization with the second data strobe signal, and output fourth alignment data;
a first data output circuit configured to latch the first to fourth alignment data, and output data of a first group in synchronization with a first strobe signal; and
a second data output circuit configured to latch the first to fourth alignment data, and output data of a second group in synchronization with a second strobe signal.

Assignees

• Sk Hynix Inc

Inventors

• Hong Yun Gi

Classifications

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title