Stacked integrated circuit devices

Patent metadata

Field	Value
Publication number	US-2025062285-A1
Application number	US-202318451971-A
Country	US
Kind code	A1
Filing date	Aug 18, 2023
Priority date	Aug 18, 2023
Publication date	Feb 20, 2025
Grant date	—

Abstract

A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

First claim

1 . A stacked integrated circuit (IC) device comprising:
a first die having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts disposed on the first face and electrically connected to the first circuitry; a second die having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts disposed on the second face and electrically connected to the second circuitry, wherein the first face is oriented toward the second face, and wherein the first die-interconnect contacts are electrically connected to the second die-interconnect contacts; a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both; and interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

2 . The stacked IC device of claim 1 , further comprising a substrate, wherein a back of the second die is coupled to a first side of the substrate and the external contacts are coupled to a second side of the substrate, and wherein the back of the second die is opposite the second face.

3 . The stacked IC device of claim 1 , wherein the first die and the second die are devoid of through-silicon vias.

4 . The stacked IC device of claim 1 , wherein the first die further comprises a first back and a first inactive region adjacent to the first back, and wherein the first back is devoid of electrical contacts.

5 . The stacked IC device of claim 1 , wherein the second die further comprises a second back and a second inactive region adjacent to the second back, and wherein the second back is devoid of electrical contacts.

6 . The stacked IC device of claim 1 , wherein the first circuitry includes one or more first transistors and the second circuitry includes one or more second transistors, and wherein the one or more first transistors are electrically connected to the one or more second transistors through the first die-interconnect contacts and the second die-interconnect contacts.

7 . The stacked IC device of claim 1 , further comprising at least one first integrated capacitor device (ICD) disposed between the first face and the set of external contacts and electrically connected to a power distribution network (PDN) of the first die.

8 . The stacked IC device of claim 1 , further comprising at least one second ICD disposed adjacent to the first die and electrically connected to a PDN of the second die.

9 . The stacked IC device of claim 1 , further comprising an interposer device comprising a plurality of conductive vias electrically connected to the redistribution layers and to a plurality of the external contacts.

10 . The stacked IC device of claim 1 , further comprising mold compound at least partially encapsulating the first die, the second die, the redistribution layers, and the interconnect conductors.

11 . The stacked IC device of claim 10 , wherein at least one of the interconnect conductors includes a through-mold via.

12 . The stacked IC device of claim 1 , further comprising at least one additional device disposed adjacent to the first die and electrically connected to the first circuitry, the second circuitry, or both, through the redistribution layers.

13 . The stacked IC device of claim 1 , further comprising at least one additional device disposed adjacent to the second die and electrically connected to the first circuitry, the second circuitry, or both, through the interconnect conductors and the redistribution layers.

14 . The stacked IC device of claim 1 , further comprising at least one additional device and second interconnect conductors, wherein the first die is disposed between the at least one additional device and the redistribution layers, and wherein additional circuitry of the at least one additional device is electrically connected to the first circuitry, the second circuitry, or both, through the second interconnect conductors and the redistribution layers.

15 . The stacked IC device of claim 1 , wherein the first die is a first chiplet and the second die is a second chiplet designed to operate in conjunction with the first chiplet.

16 . The stacked IC device of claim 15 , wherein the first circuitry includes one or more first functional circuit blocks and the second circuitry includes one or more second functional circuit blocks, and wherein the one or more first functional circuit blocks and the one or more second functional circuit blocks are operationally dependent upon one another.

17 . A method comprising:
electrically connecting a first die face-to-face with a second die using first die-interconnect contacts disposed on a first face of the first die and second die-interconnect contacts disposed on a second face of the second die, wherein a face of a die corresponds to a surface of the die bounding an active region of the die, and wherein the active region includes circuitry; forming a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both; and forming interconnect conductors external to the first die and external to the second die and electrically connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

18 . The method of claim 17 , further comprising coupling a back of the second die to a first side of a substrate, wherein the external contacts are coupled to a second side of the substrate, and wherein the back of the second die is opposite the second face.

19 . The method of claim 17 , further comprising electrically connecting an interposer device to the redistribution layers and to a plurality of the external contacts, wherein the interposer device comprises a plurality of conductive vias.

20 . The method of claim 17 , further comprising at least partially encapsulating the first die, the second die, the redistribution layers, and the interconnect conductors in a mold compound.

21 . The method of claim 20 , further comprising forming one or more through-mold vias, wherein at least one of the interconnect conductors includes a through-mold via.

22 . The method of claim 17 , further comprising electrically connecting at least one additional device to first circuitry of the first die, second circuitry of the second die, or both, through the redistribution layers.

23 . A device comprising:
a substrate having a set of external contacts on a second side; and a stacked integrated circuit (IC) device on a first side of the substrate, the stacked IC device comprising:
a first die having a first face, a first active region adjacent to the first face, first circuitry disposed in the first active region, and first die-interconnect contacts disposed on the first face and electrically connected to the first circuitry;
a second die having a second face, a second active region adjacent to the second face, second circuitry disposed in the second active region, and second die-interconnect contacts disposed on the second face and electrically connected to the second circuitry, wherein the first face is oriented toward the second face, and wherein the first die-interconnect contac

Assignees

• Qualcomm Inc

Inventors

• Li Yue
• Lane Ryan
• Sun Yangyang
• Paynter Charles David
• Lisk Durodami

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title