Molded interconnects in bridges for integrated-circuit packages

Patent metadata

Field	Value
Publication number	US-2022278084-A1
Application number	US-202017638039-A
Country	US
Kind code	A1
Filing date	Jun 26, 2020
Priority date	Sep 25, 2019
Publication date	Sep 1, 2022
Grant date	—

Abstract

Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.

First claim

1 . An integrated-circuit package apparatus, comprising:
an integrated-circuit package substrate, including a die side and a land side; a molded interconnects bridge, including:
a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the molding-mass frame is embedded in the integrated-circuit (IC) package substrate, and wherein the molding-mass frame is closer to the IC package substrate die side than to the land side:
a passive device in the molding-mass frame, wherein the passive device, occupies at least some of the same vertical space encompassed by the molding-mass frame; and
a metal build-up layer on the molding-mass frame die side, wherein the metal build-up layer is closer to the IC package substrate die side than to the land side, wherein the metal build-up layer is coupled to the passive device, and wherein the metal build-up layer includes a conductive trace, a power (Vcc) rail and a ground (Vss) rail.

2 . The integrated-circuit package apparatus of claim 1 , wherein the passive device is a first capacitor, further including:
a subsequent capacitor in the molding-mass frame.

3 . The integrated-circuit package apparatus of claim 1 , wherein the passive device is a first capacitor, further including:
a subsequent capacitor in the molding-mass frame; wherein the metal build-up layer has a first power rail coupled to the first capacitor; and wherein the metal build-up layer includes a subsequent power rail coupled to the subsequent capacitor.

4 . The integrated-circuit package apparatus of claim 1 , wherein the metal build-up layer is coupled to the die side of the integrated-circuit package substrate, further including:
a first integrated-circuit die on the IC package substrate die side, wherein the first integrated-circuit die is coupled to the passive device.

5 . The integrated-circuit package apparatus of claim 1 , wherein the metal build-up layer is coupled to the die side of the IC package substrate, wherein the passive device is a first capacitor, further including:
a first integrated-circuit die on the IC package substrate die side, wherein the first integrated-circuit die is coupled to the passive device; a subsequent capacitor in the molding-mass frame; a first integrated-circuit die on the IC package substrate die side, wherein the first integrated circuit die is coupled to the first capacitor; and a subsequent integrated-circuit die on the IC package substrate die side, wherein the subsequent integrated circuit die is coupled to the subsequent capacitor.

6 . The integrated-circuit package apparatus of claim 5 , wherein the first integrated circuit die is coupled to the subsequent integrated circuit die through the conductive trace.

7 . The integrated-circuit package apparatus of claim 1 , wherein the passive device is both coupled to the IC package substrate die side and to the land side.

8 . The integrated-circuit package apparatus of claim 1 , wherein the passive device is both coupled to the IC package substrate die side and to the land side; further including:
a first IC die on the IC package substrate die side; a subsequent IC die on the IC package substrate die side; a third IC die in a memory-die stack on the IC package substrate die side; and a fourth IC die on the IC package substrate die side.

9 . The integrated-circuit package apparatus of claim 1 , wherein the molded interconnects bridge includes the, passive device as a first capacitor, further including:
a stacked subsequent capacitor on the first capacitor, wherein power electrodes of the first and stacked subsequent capacitors make contact and form a first power rail.

10 . The integrated-circuit package apparatus of claim 1 , wherein the molded interconnects bridge includes the passive device as a first capacitor, further including:
a stacked subsequent capacitor on the first capacitor, wherein power electrodes of the first and stacked subsequent capacitors make contact and form a first power rail; and a third capacitor, wherein the stacked subsequent capacitor and the third capacitor make contact at ground electrodes to form a ground rail.

11 . The integrated-circuit package apparatus of claim 1 , wherein the molded interconnects bridge includes the passive device as a first capacitor, further including:
a stacked subsequent capacitor on the first capacitor, wherein power electrodes of the first and stacked subsequent capacitors make contact and form a first power rail; a third capacitor, wherein the stacked subsequent capacitor and the third capacitor make contact at ground electrodes to form a ground rail; a stacked fourth capacitor on the third capacitor, wherein power electrodes of the stacked fourth capacitor and the third capacitor make contact to form a second power rail; and a fifth capacitor, wherein the stacked fourth capacitor and the fifth capacitor make contact at ground electrodes to form a ground rail.

12 . The integrated-circuit package apparatus of claim 1 , wherein the molded interconnects bridge includes the passive device as a first capacitor, further including:
a stacked subsequent capacitor on the first capacitor, wherein power electrodes of the first and stacked subsequent capacitors make contact and form a first power rail; a third capacitor, wherein the stacked subsequent capacitor and the third capacitor make contact at ground electrodes to form a ground rail; a stacked fourth capacitor on the third capacitor, wherein power electrodes of the stacked forth capacitor and the third capacitor make contact to form a second power rail; a fifth capacitor, wherein the stacked fourth capacitor and the fifth capacitor make contact at ground electrodes to form a ground rail; a first IC die on the IC package substrate die side; a subsequent IC die on the IC package substrate die side; a third IC die in a memory-die stack on the IC package substrate die side; and a fourth IC die on the IC package substrate die side.

13 . A method of assembling an integrated-circuit device package, comprising:
assembling a first capacitor and a subsequent capacitor in a molding-mass frame; assembling a metal build-up layer on the molding-mass frame, wherein the metal build-up layer is coupled to the first capacitor and the subsequent capacitor, and wherein the metal build-up layer includes a conductive trace, a power (Vcc) rail and a ground (Vss) rail, to form a molded interconnects bridge; embedding the molded interconnects bridge in an integrated-circuit package substrate that has a die side and a land side, wherein the molded interconnects bridge is closer to the IC package substrate die side than to the land side; and assembling an integrated-circuit die to the IC package substrate die side, to couple first capacitor to the integrated-circuit die.

14 . The method of claim 13 , wherein the integrated-circuit die is a first IC die, further including assembling a subsequent integrated-circuit die to the IC package substrate die side, to couple the subsequent capacitor to the subsequent integrated-circuit die.

15 . The method of claim 14 , further including coupling the first IC die to the subsequent integrated-circuit die through the conductive trace.

16 . The method of claim 13 , wherein the integrated-circuit die is a first IC die, further including:
assembling a subsequent integrated-circuit die to the IC package substrate die side, to couple the subsequent capacitor to the subsequent integrated-circuit die; and assembling the land side to a board.

17 . The method of cla

Assignees

• Intel Corp

Inventors

• Ong Jenny Shio Yin
• Lim Seok Ling
• Cheah Bok Eng
• Kong Jackson Chung Peng

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title