Semiconductor packages with patterns of die-specific information

Patent metadata

Field	Value
Publication number	US-2025054776-A1
Application number	US-202418928521-A
Country	US
Kind code	A1
Filing date	Oct 28, 2024
Priority date	Aug 22, 2019
Publication date	Feb 13, 2025
Grant date	—

Abstract

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner.

First claim

What is claimed is:

1 . A method of forming a semiconductor device package, the method comprising:
positioning a semiconductor die between a first surface of the package and a second surface of the package that is opposite the first surface; forming a pattern in a designated area of the first surface, the pattern including multiple bit areas, each of the bit areas representing a first bit information or a second bit information, the pattern presenting information for operating the semiconductor die, the pattern being configured to be read by a pattern scanner.

2 . The method of claim 1 , wherein each of the bit areas includes a square shape, a triangular shape, and/or a parallelogram shape, and wherein each of the bit area includes at least one dot or at least one vacant region.

3 . The method of claim 1 , wherein the first bit information includes a value of one, and wherein the second bit information includes a value of zero.

4 . The method of claim 1 , wherein the pattern includes at least one serpentine line formed by multiple dots, and wherein a first segment of the at least one serpentine line represents the first bit information, and wherein a second segment of the at least one serpentine line represents the second bit information.

5 . The method of claim 4 , wherein the first segment of the at least one serpentine line is a horizontal segment, and wherein the second segment of the at least one serpentine line is a vertical segment or a diagonal segment.

6 . The method of claim 4 , wherein the first segment of the at least one serpentine line is a diagonal segment, and wherein the second segment of the at least one serpentine line is a horizontal segment.

7 . The method of claim 1 , wherein the pattern includes a horizontal reference line and a vertical reference line configured to indicate boundaries of the pattern.

8 . The method of claim 1 , wherein the pattern includes a reference configured to a starting point and/or an ending point for the pattern scanner to read the pattern.

9 . The method of claim 1 , wherein each of the bit areas includes a first segment representing the first bit information or a second segment representing the second bit information.

10 . The method of claim 9 , wherein the first segment includes a horizontal segment, and wherein the second segment includes a vertical segment.

11 . The method of claim 9 , wherein each of the bit areas includes a third segment representing a third bit information.

12 . The method of claim 11 , wherein each of the first segment, the second segment, and third segment includes at least one of a horizontal segment, a vertical segment, and a diagonal segment.

13 . The method of claim 1 , wherein each of the bit areas includes a first dot representing the first bit information and a second dot representing the second bit information, and wherein the first dot is larger than the second dot.

14 . A method of forming a semiconductor device, the method comprising:
forming a machine-readable pattern on an external surface of the semiconductor device, the pattern representing information for operating the semiconductor device, wherein the pattern includes a plurality of bit areas, and wherein each of plurality of bit areas includes at least one dot or at least one vacant region.

15 . The method of claim 14 , wherein the plurality of bit areas each have a shape that is triangular, rectangular, or parallelogram.

16 . The method of claim 14 , wherein the pattern includes at least one serpentine line formed by multiple dots, and wherein a first segment of the at least one serpentine line represents a first bit of information, and wherein a second segment of the at least one serpentine line represents a second bit of information.

17 . A method of reading information from a semiconductor device, the method comprising:
scanning, with a pattern scanner, a machine-readable pattern on an external surface of the semiconductor device, the pattern representing information for operating the semiconductor device, wherein the pattern includes a plurality of bit areas, and wherein each of plurality of bit areas includes at least one dot or at least one vacant region.

18 . The method of claim 17 , wherein the plurality of bit areas each have a shape that is triangular, rectangular, or parallelogram.

19 . The method of claim 17 , wherein the pattern includes at least one serpentine line formed by multiple dots, and wherein a first segment of the at least one serpentine line represents a first bit of information, and wherein a second segment of the at least one serpentine line represents a second bit of information.

20 . The method of claim 17 , wherein the pattern includes a reference configured to a starting point and/or an ending point for the pattern scanner to read the pattern.

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title