Semiconductor packages with patterns of die-specific information

Patent metadata

Field	Value
Publication number	US-12131916-B2
Application number	US-202117307273-A
Country	US
Kind code	B2
Filing date	May 4, 2021
Priority date	Aug 22, 2019
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner.

First claim

What is claimed is:

1. A semiconductor device comprising:
an external surface;
a machine-readable pattern on the external surface, the pattern representing information for operating the semiconductor device,
wherein the pattern includes a plurality of bit areas, and wherein each of plurality of bit areas includes at least one dot or at least one vacant region.

2. The semiconductor device of claim 1 , wherein the plurality of bit areas each have a shape that is triangular, rectangular, or parallelogram.

3. The semiconductor device of claim 1 , wherein the pattern includes at least one serpentine line formed by multiple dots, and wherein a first segment of the at least one serpentine line represents a first bit of information, and wherein a second segment of the at least one serpentine line represents a second bit of information.

4. The semiconductor device of claim 1 , wherein the pattern includes a horizontal reference line and a vertical reference line configured to indicate boundaries of the pattern.

5. The semiconductor device of claim 1 , wherein the pattern includes a reference configured to indicate a starting point for a pattern scanner to begin reading the pattern.

6. The semiconductor device of claim 1 , wherein the pattern includes a reference configured to indicate an ending point for a pattern scanner to stop reading the pattern.

7. The semiconductor device of claim 1 , wherein the information for operating the semiconductor device comprises a range of operating voltages, trim parameters, redundant addresses locations, instructions for controlling the semiconductor device, or a combination thereof.

8. The semiconductor device of claim 1 , wherein the pattern is a printed pattern.

9. The semiconductor device of claim 1 , wherein the pattern is stamped on, etched in, engraved in, molded on, or adhered to the semiconductor device.

10. The semiconductor device of claim 1 , wherein the external surface is comprised by a housing or casing encapsulating the semiconductor device.

11. The semiconductor device of claim 1 , wherein the external surface is a top surface of the semiconductor device.

12. The semiconductor device of claim 1 , wherein the information is encrypted in the pattern.

13. A semiconductor device package comprising:
one or more semiconductor devices;
an external surface;
a machine-readable pattern on the external surface, the pattern representing information for operating at least one of the one or more semiconductor devices,
wherein the pattern includes a plurality of bit areas, and wherein each of plurality of bit areas includes at least one dot or at least one vacant region.

14. The semiconductor device package of claim 13 , wherein the pattern includes at least one serpentine line formed by multiple dots, and wherein a first segment of the at least one serpentine line represents a first bit of information, and wherein a second segment of the at least one serpentine line represents a second bit of information.

15. The semiconductor device package of claim 13 , wherein the information for operating the at least one semiconductor device comprises a range of operating voltages, trim parameters, redundant addresses locations, instructions for controlling the at least one semiconductor device, or a combination thereof.

16. The semiconductor device package of claim 13 , wherein the pattern is a printed on, stamped on, etched in, engraved in, molded on, or adhered to the semiconductor device.

17. The semiconductor device package of claim 13 , wherein the external surface is comprised by a housing or casing encapsulating the one or more semiconductor devices.

18. A semiconductor device package comprising:
a semiconductor device;
an encapsulant having an external surface;
a machine-readable pattern on the external surface, the pattern representing information for operating the semiconductor device,
wherein the pattern includes a plurality of bit areas, and wherein each of plurality of bit areas includes at least one dot or at least one vacant region.

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title