Semiconductor packages with patterns of die-specific information

Patent metadata

Field	Value
Publication number	US-11031258-B2
Application number	US-201916548126-A
Country	US
Kind code	B2
Filing date	Aug 22, 2019
Priority date	Aug 22, 2019
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. The pattern includes multiple bit areas. Each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. The pattern is configured to be read by a pattern scanner.

First claim

I claim:

1. A semiconductor device package, comprising:
a first surface and a second surface opposite the first surface;
a semiconductor die positioned between the first and second surfaces; and
a pattern in a designated area of the first surface, the pattern including multiple bit areas, each of the bit areas representing a first bit information or a second bit information, the pattern presenting information for operating the semiconductor die, the pattern being configured to be read by a pattern scanner.

2. The semiconductor device package of claim 1 , wherein each of the bit areas includes a square shape, and wherein each of the bit area includes at least one dot or at least one vacant region.

3. The semiconductor device package of claim 1 , wherein each of the bit areas include a triangular shape, and wherein each of the bit area includes at least one dot or at least one vacant region.

4. The semiconductor device package of claim 1 , wherein each of the bit areas include a parallelogram shape, and wherein each of the bit area includes at least one dot or at least one vacant region.

5. The semiconductor device package of claim 1 , wherein the first bit information includes a value of one, and wherein the second bit information includes a value of zero.

6. The semiconductor device package of claim 1 , wherein the pattern includes at least one serpentine line formed by multiple dots, and wherein a first segment of the at least one serpentine line represents the first bit information, and wherein a second segment of the at least one serpentine line represents the second bit information.

7. The semiconductor device package of claim 6 , wherein the first segment of the at least one serpentine line is a horizontal segment, and wherein the second segment of the at least one serpentine line is a vertical segment or a diagonal segment.

8. The semiconductor device package of claim 6 , wherein the first segment of the at least one serpentine line is a diagonal segment, and wherein the second segment of the at least one serpentine line is a horizontal segment.

9. The semiconductor device package of claim 1 , wherein the pattern includes a horizontal reference line and a vertical reference line configured to indicate boundaries of the pattern.

10. The semiconductor device package of claim 1 , wherein the pattern includes a reference configured to a starting point for the pattern scanner to read the pattern.

11. The semiconductor device package of claim 1 , wherein the pattern includes a reference configured to an ending point for the pattern scanner to read the pattern.

12. The semiconductor device package of claim 1 , wherein each of the bit areas includes a first segment representing the first bit information or a second segment representing the second bit information.

13. The semiconductor device package of claim 12 , wherein the first segment includes a horizontal segment, and wherein the second segment includes a vertical segment.

14. The semiconductor device package of claim 12 , wherein each of the bit areas includes a third segment representing a third bit information.

15. The semiconductor device package of claim 14 , wherein the first segment includes a horizontal segment, and wherein the second segment includes a vertical segment, and wherein the third segment includes a diagonal segment.

16. The semiconductor device package of claim 14 , wherein the first segment includes a horizontal segment, and wherein the second segment includes a first diagonal segment, and wherein the third segment includes a second diagonal segment.

17. The semiconductor device package of claim 1 , wherein each of the bit areas includes a first dot representing the first bit information and a second dot representing the second bit information, and wherein the first dot is larger than the second dot.

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title