Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025054521-A1
Application number	US-202418928444-A
Country	US
Kind code	A1
Filing date	Oct 28, 2024
Priority date	Feb 23, 2011
Publication date	Feb 13, 2025
Grant date	—

Abstract

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

First claim

What is claimed is:

1 . A system comprising:
a connector; a volatile semiconductor memory; first to n-th nonvolatile semiconductor memories (n is an integer equal to or larger than two), each including a plurality of ball-shaped electrodes on a bottom surface; a controller configured to control the volatile semiconductor memory and the first to n-th nonvolatile semiconductor memories; first to n-th circuit elements, each including a first electrode, a second electrode, a film provided between the first electrode and the second electrode, and a coat covering the film; a multilayer wiring substrate on which the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, the first to n-th circuit elements, the controller, and the connector are mounted, the multilayer wiring substrate being shaped as a rectangle in a plan view, the connector being provided on a short side of the rectangle; and a processing circuitry being connected to the connector, wherein the first to n-th nonvolatile semiconductor memories are aligned on a line in a longitudinal direction of the multilayer wiring substrate, the controller is provided, in a plan view, between the connector and the first to n-th nonvolatile semiconductor memories, the multilayer wiring substrate includes a front surface layer with a wiring pattern formed thereon, the front surface layer being a layer on which the volatile semiconductor memory, the first to n-th nonvolatile semiconductor memories, and the controller are mounted; a rear surface layer with a wiring pattern formed thereon, the rear surface layer being a layer on which (n+1)-th to 2n-th nonvolatile semiconductor memories each including a plurality of ball-shaped electrodes on a bottom surface are mounted such that the (n+1)-th to 2n-th nonvolatile semiconductor memories are symmetric to the first to n-th nonvolatile semiconductor memories with respect to the multilayer wiring substrate, a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers having a wiring pattern formed thereon, first to n-th signal lines that connect the controller to the first to n-th circuit elements, respectively; (n+1)-th to 2n-th signal lines that connect the first to n-th circuit elements to the first to n-th nonvolatile semiconductor memories, respectively, the (n+1)-th to 2n-th signal lines having a part that passes through the internal wiring layers; and (2n+1)-th to 3n-th signal lines that branch from the (n+1)-th to 2n-th signal lines and connect the (n+1)-th to 2n-th nonvolatile semiconductor memories, respectively.

2 . The system according to claim 1 , wherein
each of the (n+1)-th to 2n-th signal lines includes a signal line formed on a first wiring layer that is one of the plurality of internal wiring layers and a signal line formed on a second wiring layer that is one of the plurality of internal wiring layers, the second wiring layer being a different wiring layer from the first wiring layer.

3 . The system according to claim 2 , wherein
each of the (n+1)-th to 2n-th signal lines includes a part that extends almost perpendicular to a front surface of the multilayer wiring substrate to connect the signal line formed on the first wiring layer and the signal line formed on the second wiring layer.

4 . The system according to claim 1 , wherein
the multilayer wiring substrate is configured such that, in a plan view, a region provided with a (3n+1)-th signal line and a region provided with the volatile semiconductor memory do not overlap each other, the (3n+1)-th signal line connecting the controller to the connector.

5 . The system according to claim 4 , wherein
the (3n+1)-th signal line is a SATA signal line.

6 . The system according to claim 4 , wherein the connector includes an electrode to be connected to the processing circuitry on the rear surface layer of the multilayer wiring substrate, and
the (3n+1)-th signal line includes a part connected to the electrode of the connector through the rear surface layer of the multilayer wiring substrate and a part formed in one of the plurality of internal wiring layers.

7 . The system according to claim 1 , wherein the volatile semiconductor memory and the connector are provided on the same side of the multilayer wiring substrate relative to the first to n-th nonvolatile semiconductor memories in a plan view.

8 . The system according to claim 1 , further comprising:
a temperature sensor.

9 . The system according to claim 1 , wherein
each the first to n-th signal lines includes a first part, a second part, and a third part, the first part is formed on the front surface layer, the second part is formed on the rear surface layer, and the third part extends almost perpendicular to a front surface of the multilayer wiring substrate to connect the first part and the second part.

10 . The system according to claim 1 , wherein
the number of layers in the multilayer wiring substrate is eight.

11 . The system according to claim 1 , wherein
a k-th nonvolatile semiconductor memory (k is an integer satisfying 1≤k≤n) of the first to n-th nonvolatile semiconductor memories is configured to determine whether to operate in response to a signal from an (n+k)-th signal line of the (n+1)-th to 2n-th signal lines based on a chip enable signal of the k-th nonvolatile semiconductor memory.

12 . The system according to claim 1 , further comprising:
a power supply circuit that is mounted on the multilayer wiring substrate, wherein the processing circuitry is configured to input power into the connector, the connector is configured to supply the input power to the power supply circuit, and the power supply circuit is configured to generate internal voltages on the basis of the supplied power and to supply the generated internal voltages to the first to n-th nonvolatile semiconductor memories.

13 . The system according to claim 1 , wherein
the integer n is four.

Assignees

• Kioxia Corp

Inventors

• Sugita Masato
• Kimura Naoki
• Kimura Daisuke

Classifications

• G06F2213/0032

  Serial ATA [SATA] · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G11C14/0018

  whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C16/04

  using variable threshold transistors, e.g. FAMOS · CPC title