Semiconductor device

Patent metadata

Field	Value
Publication number	US-10056119-B2
Application number	US-201715646360-A
Country	US
Kind code	B2
Filing date	Jul 11, 2017
Priority date	Feb 23, 2011
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

First claim

What is claimed is:

1. A semiconductor device comprising:
first to n-th nonvolatile semiconductor elements, where n is an integer greater than or equal to two;
(n +1)th to 2n-th nonvolatile semiconductor elements;
first to n-th resistive elements;
a controller that controls the first to 2n-th nonvolatile semiconductor elements;
first to n-th signal lines that connect the controller to each of the first to n-th resistive elements;
(n +1)th to 2n-th signal lines that connect the first to n-th resistive elements to the first to n-th nonvolatile semiconductor elements, respectively;
(2n +1)th to 3n-th signal lines that branch from the (n +1)th to 2n-th signal lines, the (2n +1)th to 3n-th signal lines being connected to the (n +1)th to 2n-th nonvolatile semiconductor elements, respectively;
a connector that allows connection to an external device; and
a substrate on which the first to 2n-th nonvolatile semiconductor elements, the first to n-th resistive elements, the controller, and the connector are mounted, wherein
the substrate includes:
a front surface layer that includes a wiring pattern formed on a front surface of the substrate, the front surface layer being a layer on which the first to n-th nonvolatile semiconductor elements and the first to n-th resistive elements are mounted; and
a rear surface layer that includes a wiring pattern formed on a rear surface of the substrate, the rear surface layer being a layer on which the (n +1)th to 2n-th nonvolatile semiconductor elements are mounted, and

the first to n-th nonvolatile semiconductor elements and the (n +1)th to 2n-th nonvolatile semiconductor elements are disposed symmetrically on opposite sides of the substrate.

2. The semiconductor device according to claim 1 , wherein n is four.

3. The semiconductor device according to claim 1 , wherein
the substrate includes a first edge and a second edge, the second edge being perpendicular to the first edge in a plan view,
the connector is provided on the first edge of the substrate, and
the first to n-th nonvolatile semiconductor elements are provided on a side opposite to the connector with respect to the controller in a plan view.

4. The semiconductor device according to claim 3 , further comprising:
a volatile semiconductor element that is provided on the same side as the connector relative to the first to n-th nonvolatile semiconductor elements in a plan view.

5. The semiconductor device according to claim 1 , further comprising:
a temperature sensor mounted on the front surface layer.

6. The semiconductor device according to claim 1 , further comprising:
a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers including a wiring pattern, wherein
at least one of the (n +k)th signal line and the (2n +k)th signal line includes a signal line formed on a first wiring layer, k being all integers greater than or equal to one and less than or equal to n, the first wiring layer being one of the plurality of internal wiring layers.

7. The semiconductor device according to claim 6 , wherein at least one of the (n +k)th signal line and the (2n +k)th signal line includes a signal line formed on a second wiring layer, the second wiring layer being one of the plurality of internal wiring layers, the second wiring layer being a different wiring layer from the first wiring layer.

8. The semiconductor device according to claim 7 , wherein at least one of the (n +k)th signal line and the (2n +k)th signal line includes a part that extends almost perpendicular to the front surface of the substrate to connect the signal line formed on the first wiring layer and the signal line formed on the second wiring layer.

9. The semiconductor device according to claim 1 , wherein
the 1-th signal line includes a first part, a second part, and a third part, 1being all integers greater than or equal to one and less than or equal to n,
the first part is formed on the front surface layer,
the second part is formed on the rear surface layer, and
the third part extends almost perpendicular to the front surface of the substrate to connect the first part and the second part.

10. The semiconductor device according to claim 1 , wherein the number of layers in the substrate is eight.

11. The semiconductor device according to claim 3 , wherein
the substrate includes a third edge, the third edge being perpendicular to the first edge and parallel to the second edge in a plan view,
n is an even number,
first to n/2-th nonvolatile semiconductor elements among the first to n-th nonvolatile semiconductor elements are disposed toward the second edge of the substrate, and
(n/2+1)th to n-th nonvolatile semiconductor elements among the first to n-th nonvolatile semiconductor elements are disposed toward the third edge of the substrate.

12. The semiconductor device according to claim 1 , wherein the nonvolatile semiconductor elements are NAND-type flash memories.

13. The semiconductor device according to claim 1 , further comprising:
a power supply circuit that is provided on the first main surface, wherein
the power supply circuit is configured to generate internal voltages on the basis of power supplied from the outside via the connector and to supply the generated internal voltages to the first to n-th nonvolatile semiconductor elements.

14. The semiconductor device according to claim 1 , wherein
the connector is connectable to a host, and
the connector supplies power input from the host to the power supply circuit.

Assignees

• Toshiba Memory Corp

Inventors

• Sugita Masato
• Kimura Naoki
• Kimura Daisuke

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G06F16/9535

  Search customisation based on user profiles and personalisation · CPC title