Semiconductor device

Patent metadata

Field	Value
Publication number	US-11735230-B2
Application number	US-202117565713-A
Country	US
Kind code	B2
Filing date	Dec 30, 2021
Priority date	Feb 23, 2011
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

First claim

What is claimed is:

1. A system comprising:
a connector;
a first nonvolatile semiconductor memory;
a second nonvolatile semiconductor memory;
a volatile semiconductor memory;
a circuit element including a film and a coat, the film being provided between a first electrode and a second electrode, the coat covering the film;
a controller configured to control the first nonvolatile semiconductor memory, the second nonvolatile semiconductor memory, and the volatile semiconductor memory;
a first signal line that connects the controller to the circuit element;
a second signal line that connects the circuit element to the first nonvolatile semiconductor memory;
a via-hole;
a third signal line that branches by the via-hole from the second signal line, the third signal line being connected to the second nonvolatile semiconductor memory;
a substrate on which the first nonvolatile semiconductor memory, the second nonvolatile semiconductor memory, the circuit element, the controller, and the connector are mounted; and
a processing circuitry being connected to the connector, wherein the substrate includes:
a front surface layer that includes a wiring pattern formed on a front surface of the substrate, the front surface layer being a layer on which the first nonvolatile semiconductor memory and the circuit element are mounted;
a rear surface layer that includes a wiring pattern formed on a rear surface of the substrate, the rear surface layer being a layer on which the second nonvolatile semiconductor memory is mounted; and
a plurality of internal wiring layers that is provided between the front surface layer and the rear surface layer, the plurality of internal wiring layers including a wiring pattern,

the second signal line includes a signal line formed on a first wiring layer that is one of the plurality of internal wiring layers and a signal line formed on a second wiring layer that is one of the plurality of internal wiring layers, the second wiring layer being a different wiring layer from the first wiring layer, and
the volatile semiconductor memory and the connector are provided on the same side of the substrate relative to the first nonvolatile semiconductor memory or the second nonvolatile semiconductor memory in a plan view.

2. The system according to claim 1 , wherein
the second signal line includes a part that extends almost perpendicular to the front surface of the substrate to connect the signal line formed on the first wiring layer and the signal line formed on the second wiring layer.

3. The system according to claim 1 , wherein
the substrate is configured such that, in a plan view, a region provided with the volatile semiconductor memory and a region provided with a fourth signal line do not overlap each other, the fourth signal line connecting the controller to the connector.

4. The system according to claim 2 , wherein
the substrate is configured such that, in a plan view, a region provided with the volatile semiconductor memory and a region provided with a fourth signal line do not overlap each other, the fourth signal line connecting the controller to the connector.

5. The system according to claim 3 , wherein the fourth signal line is a SATA signal line.

6. The system according to claim 3 , wherein the connector includes an electrode to be connected to the processing circuitry on the rear surface of the substrate, and
the fourth signal line includes a part connected to the electrode of the connector through the rear surface layer of the substrate and a part formed in one of the plurality of internal wiring layers.

7. The system according to claim 1 , wherein
the first nonvolatile semiconductor memory includes ball-shaped electrodes on a bottom surface of the first nonvolatile semiconductor memory,
the first nonvolatile semiconductor memory is connected to the substrate through the ball-shaped electrodes of the first nonvolatile semiconductor memory,
the second nonvolatile semiconductor memory includes ball-shaped electrodes on a bottom surface of the second nonvolatile semiconductor memory, and
the second nonvolatile semiconductor memory is connected to the substrate through the ball-shaped electrodes of the second nonvolatile semiconductor memory.

8. The system according to claim 2 , wherein
the first nonvolatile semiconductor memory includes ball-shaped electrodes on a bottom surface of the first nonvolatile semiconductor memory,
the first nonvolatile semiconductor memory is connected to the substrate through the ball-shaped electrodes of the first nonvolatile semiconductor memory,
the second nonvolatile semiconductor memory includes ball-shaped electrodes on a bottom surface of the second nonvolatile semiconductor memory, and
the second nonvolatile semiconductor memory is connected to the substrate through the ball-shaped electrodes of the second nonvolatile semiconductor memory.

9. The system according to claim 1 , wherein
the substrate includes a first edge and a second edge, the second edge being perpendicular to the first edge in a plan view,
the connector is provided on the first edge of the substrate, and
the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory are provided opposite to the connector across the controller in a plan view.

10. The system according to claim 2 , wherein
the substrate includes a first edge and a second edge, the second edge being perpendicular to the first edge in a plan view,
the connector is provided on the first edge of the substrate, and
the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory are provided opposite to the connector across the controller in a plan view.

11. The system according to claim 1 , further comprising:
a temperature sensor.

12. The system according to claim 1 , wherein
the first signal line includes a first part, a second part, and a third part,
the first part is formed on the front surface layer,
the second part is formed on the rear surface layer, and
the third part extends almost perpendicular to the front surface of the substrate to connect the first part and the second part.

13. The system according to claim 2 , wherein
the first signal line includes a first part, a second part, and a third part,
the first part is formed on the front surface layer,
the second part is formed on the rear surface layer, and
the third part extends almost perpendicular to the front surface of the substrate to connect the first part and the second part.

14. The system according to claim 3 , wherein
the first signal line includes a first part, a second part, and a third part,
the first part is formed on the front surface layer,
the second part is formed on the rear surface layer, and
the third part extends almost perpendicular to the front surface of the substrate to connect the first part and the second part.

15. The system according to claim 1 , wherein
the first nonvolatile semiconductor memory and the second nonvolatile semiconductor memory is disposed symmetrically on opposite sides of the substrate.

16. The system according to claim 1 , wherein
the number of layers in the substrate is eight.

17. The system according to claim 1 , wherein
the first nonvolatile semiconductor memory is configured to determine whether to operate in response to a signal from the second signal line based on a chip enable signal of the first nonvolatile semiconductor memory.

18. The system according to claim 1 , wherein
the first nonvolatile semiconductor memory and

Assignees

• Kioxia Corp

Inventors

• Sugita Masato
• Kimura Naoki
• Kimura Daisuke

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F16/9535

  Search customisation based on user profiles and personalisation · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title