Memory device including 2-transistor memory cell structure for neural network

Patent metadata

Field	Value
Publication number	US-2025029638-A1
Application number	US-202418778321-A
Country	US
Kind code	A1
Filing date	Jul 19, 2024
Priority date	Jul 20, 2023
Publication date	Jan 23, 2025
Grant date	—

Abstract

Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory cell and a second memory cell, each of the first and second memory cells including a first transistor including a first region and a first charge storage structure separated from the first region; a second transistor including a second region formed over the first charge storage structure; a first data line coupled to the first memory cell configured to provide a first sum based on current on the first data line during a memory operation; a second data line coupled to the second memory cell configured to provide a second sum based on current on the second data line during the memory operation; and an output circuit to provide output information based on values of the first and second sums.

First claim

What is claimed is:

1 . An apparatus comprising:
a first memory cell including a first transistor and a second transistor, the first transistor including a first region and a first charge storage structure separated from the first region, the second transistor including a second region formed over the first charge storage structure, the first and second regions including materials of different conductivity types; a second memory cell including a first additional transistor and a second additional transistor, the first additional transistor including a first additional region and a second charge storage structure separated from the first additional region, the second additional transistor including a second additional region formed over the second charge storage structure, the first and second additional regions including materials of different conductivity types; a first data line coupled to the first memory cell configured to provide a first sum based on current on the first data line during a memory operation; a second data line coupled to the second memory cell configured to provide a second sum based on current on the second data line during the memory operation; and an output circuit to provide output information based on values of the first and second sums.

2 . The apparatus of claim 1 , further comprising:
a first conductive structure separated from the first region, the first charge storage structure, and the second region, the first conductive structure forming part of a gate of the first transistor and the second transistor; and a second conductive structure separated from the first additional region, the second charge storage structure, and the second additional region, the second conductive structure forming part of a gate of the first additional transistor and the second additional transistor.

3 . The apparatus of claim 1 , wherein the first transistor and the first additional transistor are coupled to a common conductive structure.

4 . The apparatus of claim 3 , wherein the common conductive structure is coupled to a ground connection of the apparatus.

5 . The apparatus of claim 1 , wherein:
the first region includes a channel region of the first transistor, and the second region includes a channel region of the second transistor; and the first additional region includes a channel region of the first additional transistor, and the second additional region includes a channel region of the second additional transistor.

6 . The apparatus of claim 1 , wherein:
the first data line is coupled to the first region and the second region; and the second data line is coupled to the first additional region and the second additional region.

7 . The apparatus of claim 1 , wherein each of the first region and the first additional region includes a semiconductor material.

8 . The apparatus of claim 1 , wherein each of the second region and the second additional region includes a semiconducting oxide material.

9 . The apparatus of claim 1 , wherein the apparatus comprises a memory device, the first memory cell is included in a first memory array, and the second memory cell is included in a second memory array of the memory device.

10 . The apparatus of claim 1 , wherein the apparatus comprises a memory device, the first memory cell is included in a first deck of memory cells of the memory device, and the second memory cell is included in a second deck of the memory device, and the first deck of memory cells and the second deck of memory cells are located in different levels of the memory device.

11 . An apparatus comprising:
a first memory cell including a first transistor and a second transistor, the first transistor including a first region and a first charge storage structure separated from the first region, the second transistor including a second region formed over the first charge storage structure, the first and second regions including materials of different conductivity types; a second memory cell including a first additional transistor and a second additional transistor, the first additional transistor including a first additional region and a second charge storage structure separated from the first additional region, the second additional transistor including a second additional region formed over the second charge storage structure, the first and second additional regions including materials of different conductivity types; and a memory control unit including circuitry configured to operate on the first and second memory cells to obtain multiply-accumulate information based on input information provided to access lines coupled to the first and second memory cells and weight information stored in the first and second memory cells.

12 . The apparatus of claim 11 , wherein the memory control unit is configured to accumulate the information based on a first result of a first multiply-accumulate information and a second result of a second multiply-accumulate information, wherein the first multiply-accumulate information is provided from a first data line coupled to the first memory cell, and the second multiply-accumulate information is provided from a second data line coupled to the second memory cell.

13 . The apparatus of claim 11 , wherein the weight information is binary coded weight information.

14 . The apparatus of claim 11 , wherein each of the first region and the first additional region includes polysilicon, and each of the second region and the second additional region includes a semiconducting oxide material.

15 . The apparatus of claim 11 , wherein each of the first region and the first additional region includes a polysilicon, and each of the second region and the second additional region includes a semiconducting oxide material.

16 . The apparatus of claim 11 , wherein each of the first region and the first additional region includes a p-type conductivity material, and each of the second region and the second additional region includes an n-type conductivity material.

17 . The apparatus of claim 11 , wherein each of the second region and the second additional region includes at least one of zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO x , In 2 O 3 ), tin oxide (SnO 2 ), titanium oxide (TiOx), zinc oxide nitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), indium zinc oxide (In x Zn y O z ), indium gallium zinc oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), hafnium indium zinc oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a ), zirconium zinc tin oxide (Zr x Zn y Sn z O a ), indium gallium silicon oxide (InGaSiO), and gallium phosphide (GaP).

18 . A method comprising:
obtaining first multiply-accumulate information from a first data line of a memory device, the first multiply-accumulate information based at least in part on first input information provided to a first access line coupled to a gate of a first transistor and a gate of second transistor of a first memory cell coupled to the first data line and based on first weight information associated with a neural network; obtaining second multiply-accumulate information from a second data line of the memory device, the second multiply-accumul

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Sarpatwari Karthik
• Calderoni Alessandro
• Ramaswamy Durai Vishak Nirmal
• Gao Yunfei

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title

• H10B41/70

  the floating gate being an electrode shared by two or more components · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• H10B12/488

  Word lines · CPC title