Three-dimensional memory device including inclined word line contact strips and methods of forming the same
US-2024414916-A1 · Dec 12, 2024 · US
Three-dimensional (3d) semiconductor memory device
US2024341099A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2024341099-A1 |
| Application number | US-202418750042-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 21, 2024 |
| Priority date | May 18, 2020 |
| Publication date | Oct 10, 2024 |
| Grant date | — |
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Abstract
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A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region, a first electrode structure and a second electrode structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure including stacked sacrificial layers, vertical channel structures penetrating the first and second electrode structures, a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure, and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern is greater than a maximum width of the separation structure in the second direction.
First claim
Opening claim text (preview).
What is claimed is: 1 . A three-dimensional (3D) semiconductor memory device comprising: a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region between the first row decoder region and the second row decoder region; a first electrode structure and a second electrode structure on the peripheral circuit structure, wherein the first electrode structure and the second electrode structure are spaced apart in a first direction and each respectively includes stacked electrodes; a mold structure on the peripheral circuit structure, wherein the mold structure is disposed between the first electrode structure and the second electrode structure and includes stacked sacrificial layers; vertical channel structures penetrating the first electrode structure and the second electrode structure; a separation insulating pattern provided between the first electrode structure and the mold structure and penetrating the mold structure; and a separation structure intersecting the first electrode structure in the first direction and extending to the separation insulating pattern, wherein a maximum width of the separation insulating pattern in a second direction is greater than a maximum width of the separation structure in the second direction.
Assignees
Inventors
Classifications
- H10B43/27Primary
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
characterised by the top-view layout · CPC title
comprising only one type of peripheral transistor · CPC title
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
characterised by the top-view layout · CPC title
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- What does patent US2024341099A1 cover?
- A 3D semiconductor memory device includes a peripheral circuit structure including a first row decoder region, a second row decoder region, and a control circuit region, a first electrode structure and a second electrode structure, spaced apart in a first direction, and each including stacked electrodes, a mold structure including stacked sacrificial layers, vertical channel structures penetrat…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10B43/27. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Oct 10 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).