Digital phase-locked loop

Patent metadata

Field	Value
Publication number	US-11646743-B1
Application number	US-202217654073-A
Country	US
Kind code	B1
Filing date	Mar 9, 2022
Priority date	Mar 9, 2022
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A digital phase-locked loop (PLL) includes a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO). The DCO generates a PLL clock signal and various sampling clock signals that are mesochronous. The TDC samples a phase difference between a reference clock signal and a frequency-divided version of the PLL clock signal based on the sampling clock signals and various enable signals. The enable signals are generated based on a calibration of the digital PLL. Each enable signal is associated with a sampling clock signal and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference. Further, the TDC generates control data indicative of the sampled phase difference. The DCO generates the PLL clock signal and the sampling clock signals based on the control data until the digital PLL is in a phase-locked state.

First claim

The invention claimed is:

1. A digital phase-locked loop (PLL), comprising:
a digitally controlled oscillator (DCO) configured to generate (i) a PLL clock signal and (ii) a plurality of sampling clock signals that is mesochronous; and
a time-to-digital converter (TDC) that is coupled to the DCO, and configured to:
sample, based on the plurality of sampling clock signals and a plurality of enable signals, a phase difference between (i) a reference clock signal and (ii) a feedback clock signal that is derived from the PLL clock signal, wherein the plurality of enable signals is generated based on a calibration of the digital PLL, and wherein each enable signal of the plurality of enable signals is associated with a sampling clock signal of the plurality of sampling clock signals and indicates whether the associated sampling clock signal is to be utilized for sampling the phase difference between the reference clock signal and the feedback clock signal; and
generate control data indicative of the sampled phase difference, wherein after the digital PLL is calibrated, the DCO generates the plurality of sampling clock signals and the PLL clock signal based on the control data such that the phase difference between the reference clock signal and the feedback clock signal is less than a tolerance limit associated with the digital PLL.

2. The digital PLL of claim 1 , wherein after the digital PLL is calibrated, the DCO generates the plurality of sampling clock signals and the PLL clock signal further based on calibration data, and wherein the calibration data is generated based on a coarse frequency matching between the reference clock signal and the feedback clock signal during the calibration of the digital PLL.

3. The digital PLL of claim 1 , further comprising a storage element configured to store a mapping between (i) a plurality of predefined frequencies, (ii) a predefined calibration data set, and (iii) a plurality of predefined values, wherein each predefined value of the plurality of predefined values is indicative of a number of sampling clock signals of the plurality of sampling clock signals that are to be utilized for sampling the phase difference between the reference clock signal and the feedback clock signal.

4. The digital PLL of claim 3 , further comprising a processing circuit that is coupled to the storage element, and configured to:
compare (i) a locking frequency of the digital PLL with each predefined frequency of the plurality of predefined frequencies and (ii) calibration data with each predefined data of the predefined calibration data set, wherein the calibration data is generated based on a coarse frequency matching between the reference clock signal and the feedback clock signal during the calibration of the digital PLL; and
identify, from the plurality of predefined values to facilitate the generation of the plurality of enable signals, a first predefined value that is associated with the locking frequency of the digital PLL and the calibration data, wherein the first predefined value is identified based on the comparison of the locking frequency of the digital PLL with each predefined frequency of the plurality of predefined frequencies and the comparison of the calibration data with each predefined data of the predefined calibration data set.

5. The digital PLL of claim 4 , wherein the feedback clock signal is derived from the PLL clock signal such that a frequency of the feedback clock signal corresponds to a result of a division of a frequency of the PLL clock signal by a division factor, and wherein the processing circuit is further configured to determine the locking frequency of the digital PLL based on a product of a frequency of the reference clock signal and the division factor.

6. The digital PLL of claim 4 , wherein the processing circuit is further coupled to the TDC, and configured to:
generate the plurality of enable signals based on the first predefined value such that one or more enable signals of the plurality of enable signals are asserted and remaining enable signals of the plurality of enable signals are de-asserted; and
provide the plurality of enable signals to the TDC to control the TDC after the calibration of the digital PLL, wherein the TDC samples the phase difference between the reference clock signal and the feedback clock signal based on one or more sampling clock signals of the plurality of sampling clock signals that are associated with the one or more enable signals, respectively.

7. The digital PLL of claim 4 , wherein a loop transfer function of the digital PLL is controlled based on a gain of the DCO and the first predefined value.

8. The digital PLL of claim 1 , wherein the TDC comprises a phase frequency detector configured to receive the reference clock signal and the feedback clock signal, and generate a start signal and a stop signal to sample the phase difference between the reference clock signal and the feedback clock signal, wherein the start signal is asserted based on an assertion of one of a group consisting of the reference clock signal and the feedback clock signal, wherein when the start signal is asserted based on the assertion of the reference clock signal, the stop signal is asserted based on the assertion of the feedback clock signal, and when the start signal is asserted based on the assertion of the feedback clock signal, the stop signal is asserted based on the assertion of the reference clock signal, and wherein a time duration between the assertion of the start signal and the assertion of the stop signal is indicative of the phase difference between the reference clock signal and the feedback clock signal.

9. The digital PLL of claim 8 , wherein the TDC further comprises:
a plurality of counters that is coupled to the phase frequency detector and the DCO, and configured to:
receive the start signal, the stop signal, the plurality of enable signals, and the plurality of sampling clock signals, wherein each counter of the plurality of counters is activated based on an assertion of an associated enable signal of the plurality of enable signals; and
generate a plurality of count values that is indicative of the sampled phase difference between the reference clock signal and the feedback clock signal, wherein the plurality of count values is incremented based on the assertion of the start signal and transitions of the plurality of sampling clock signals, and wherein the plurality of counters is halted based on the assertion of the stop signal; and

an adder that is coupled to the plurality of counters, and configured to generate the control data based on the plurality of count values such that the control data corresponds to a sum of the plurality of count values.

10. The digital PLL of claim 1 , further comprising a digital loop filter that is coupled to the TDC and the DCO, and configured to receive the control data from the TDC, generate filtered control data, and provide the filtered control data to the DCO to facilitate the generation of the plurality of sampling clock signals and the PLL clock signal after the digital PLL is calibrated.

11. The digital PLL of claim 1 , wherein the DCO comprises a ring oscillator configured to generate a plurality of PLL clock signals based on a sum of (i) a first drive current that is derived from calibration data and (ii) a second drive current that is derived from the control data, wherein the plurality of PLL clock signals comprises the PLL clock signal, wherein the calibration data is generated based on a coarse frequency matching between the reference clock signal and the feedback clock signal during the calibration of the digital PLL, and wherein the plurality of sampling clock s

Assignees

• Nxp Usa Inc

Inventors

• Sabharwal Pawan
• Sinha Anand Kumar
• Thakur Krishna
• Jain Deependra Kumar

Classifications

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/103 Primary

  the additional signal being a digital signal · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/1075

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title