Spur canceller with multiplier-less correlator

Patent metadata

Field	Value
Publication number	US-10680622-B2
Application number	US-201816143711-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A spur cancellation circuit uses low cost multipliers in a correlation circuit. Each low cost multiplier multiplies a value of a sense node by a representation of a sinusoid and supplies a multiplication result. A compare circuit compares the sinusoid to one or more threshold values and supplies a compare indication. A multiplexer selects between two or more inputs including a positive value of the sense node and a negative value of the sense node, based on the compare result. A single threshold at zero converts the sinusoid to a square wave and the multiplexer supplies either the positive value or the negative value, which is equivalent to multiplying the value at the sense node by 1 or −1 depending on the sign of the sinusoid. Two thresholds may be used to represent the sinusoid with three values, the positive value, the negative value, or zero.

First claim

What is claimed is:

1. A method comprising:
generating a sinusoidal signal;
comparing the sinusoidal signal to a first threshold and generating a compare indication;
selecting a first input signal to a multiplexer circuit as a multiplexer output signal responsive to the compare indication indicating the sinusoidal signal is above the first threshold;
selecting a second input signal to the multiplexer circuit as the multiplexer output signal responsive to the compare indication indicating the sinusoidal signal is below the first threshold; and
wherein the compare indication indicates a sign of the sinusoidal signal.

2. The method as recited in claim 1 wherein the first input signal is a value of a sense node in a phase-locked loop.

3. The method as recited in claim 1 further comprising selecting the first input signal or the second input signal according to the sign, where the first input signal is a value of a sense node and the second input signal is a negative value of the sense node.

4. The method as recited in claim 3 wherein the comparing and the multiplexer circuit convert the sinusoidal signal to a square wave and the multiplexer output signal provides the value of the sense node multiplied by the square wave having a value of one or minus one.

5. The method as recited in claim 3 wherein the sinusoidal signal is at a frequency that is a harmonic of a target frequency of a spur to be canceled and the method further includes:
accumulating an error signal that is an output of the multiplexer circuit in an accumulator circuit;
scaling an accumulator output of the accumulator circuit by a scale factor based on the harmonic;
adjusting a second accumulated signal corresponding to a second error signal indicating a correlation between the value of the sense node and a second sinusoidal signal at the target frequency; and
generating a weighting factor for the second sinusoidal signal for use in generating a spur cancellation signal to cancel the spur at the target frequency.

6. A method comprising:
generating a sinusoidal signal;
comparing the sinusoidal signal to a first threshold and a second threshold;
generating a compare indication, wherein the compare indication indicates whether the sinusoidal signal is above the first threshold, between the first threshold and the second threshold, or below the second threshold;
selecting a first input signal to a multiplexer circuit as a multiplexer output signal responsive to the compare indication indicating the sinusoidal signal is above the first threshold; and
selecting a second input signal to the multiplexer circuit as the multiplexer output signal responsive to the compare indication indicating the sinusoidal signal is below the second threshold.

7. The method as recited in claim 6 further comprising:
selecting a third input signal to the multiplexer circuit as the multiplexer output signal responsive to the compare indication indicating the sinusoidal signal is below the first threshold and above the second threshold.

8. The method as recited in claim 7 wherein the first input signal is a positive value of a sense node, the second input signal is a negative value of the sense node, and the third input signal is zero.

9. An apparatus comprising:
a compare circuit to compare a sinusoidal signal to one or more threshold values and supply a compare indication;
a multiplexer circuit coupled to select between at least a first input signal and a second input signal to the multiplexer circuit as a multiplexer output signal according to the compare indication; and
an accumulator to accumulate the multiplexer output signal for use in generating a spur cancellation signal.

10. The apparatus as recited in claim 9 wherein the first input signal is a value of a sense node and the second input signal is a negative value of the sense node.

11. The apparatus as recited in claim 10 wherein the multiplexer circuit is part of a correlator circuit that correlates the sinusoidal signal to the value of the sense node as part of generating the spur cancellation signal.

12. The apparatus as recited in claim 10 wherein the compare indication indicates a sign of the sinusoidal signal and wherein the multiplexer circuit is configured to select the first input signal or the second input signal according to the sign.

13. The apparatus as recited in claim 12 wherein the compare circuit and the multiplexer circuit provide a function equivalent to multiplying the value of the sense node by a square wave having a value of one or minus one.

14. The apparatus as recited in claim 12 wherein the sinusoidal signal is at a frequency that is a harmonic of a target frequency of a spur to be canceled and the apparatus further comprises:
an accumulator circuit to accumulate the multiplexer output signal as an error signal;
a scaling circuit to scale an accumulator output of the accumulator circuit by a scale factor based on the harmonic;
a summing circuit to adjust a second accumulated signal corresponding to a second error signal indicating correlation between the value of the sense node and a second sinusoidal signal at the target frequency; and
wherein a weighting factor is generated for the second sinusoidal signal using an output of the summing circuit, the weighting factor for use in generating a spur cancellation signal to cancel the spur at the target frequency.

15. The apparatus as recited in claim 9 ,
wherein the one or more threshold values includes a first threshold and a second threshold and the compare circuit compares the sinusoidal signal to the first threshold and to the second threshold; and
wherein the compare circuit provides the compare indication to the multiplexer circuit as a select signal, the compare indication indicating whether the sinusoidal signal is above the first threshold, between the first and second threshold, or below the second threshold.

16. The apparatus as recited in claim 15 ,
wherein the multiplexer circuit supplies the first input signal as the multiplexer output signal responsive to the compare indication indicating that the sinusoidal signal is above the first threshold;
wherein the multiplexer circuit supplies the second input signal to the multiplexer circuit as the multiplexer output signal responsive to the compare indication indicating that the sinusoidal signal is below the second threshold;
wherein the multiplexer circuit is responsive to supply a third input signal to the multiplexer circuit as the multiplexer output signal responsive to the compare indication indicating the sinusoidal signal is below the first threshold and above the second threshold; and
wherein the first input signal is a positive value of a sense node in a phase-locked loop, the positive value of the sense node being supplied to a loop filter, the second input signal is a negative value of the sense node, and the third input signal is zero.

17. A spur cancellation circuit comprising:
a correlation circuit having a first circuit to supply a multiplication result equivalent to a multiplication of a value of a sense node by a signal corresponding to a sinusoidal signal, wherein the first circuit includes,
a compare circuit to compare the sinusoidal signal to one or more threshold values and supply a compare indication; and
a multiplexer circuit coupled to select between at least a value of the sense node and a negative value of the sense node as a multiplexer output signal according to the compare indication, the multiplexer output signal being the multiplication result.

18. The s

Assignees

• Silicon Lab Inc

Inventors

• Monk Timothy A
• Thirugnanam Rajesh

Classifications

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title