Asymmetric transistor devices

Patent metadata

Field	Value
Publication number	US-2024284663-A1
Application number	US-202418440348-A
Country	US
Kind code	A1
Filing date	Feb 13, 2024
Priority date	Feb 17, 2023
Publication date	Aug 22, 2024
Grant date	—

Abstract

A variety of applications can include an apparatus having one or more pairs of transistors sharing a common source region that provide asymmetric transistor devices. The drains of the transistors of a pair sharing a common source region can be structured with the source junction depth being shallower than the drain junction depth of the drain region of at least one of the transistors of the pair. Tilted implantation can be used to extend a drain junction depth beyond the distance of the source junction depth by implanting additional dopants. The extension of the drain junction depth can be accomplished without additional masks being used in processing to dope only a drain region and skip doping on a corresponding source region.

First claim

What is claimed is:

1 . An electronic device comprising:
a first transistor including a first drain region and a source region; and a second transistor including the source region and a second drain region, the source region having a source junction depth shallower than a first drain junction depth of the first drain region and shallower than a second drain junction depth of the second drain region.

2 . The electronic device of claim 1 , wherein the first drain junction depth is at least twice the source junction depth.

3 . The electronic device of claim 1 , wherein the electronic device includes a p-type substrate in which the first drain region, the second drain region, and the source region are disposed, with the first drain region being a n-type region, the second drain region being a n-type region, and the source region being a n-type region.

4 . The electronic device of claim 1 , wherein the first drain region is separated from a third drain region of a third transistor by a first isolation region and the second drain region is separated from a fourth drain region of a fourth transistor by a second isolation region.

5 . The electronic device of claim 1 , wherein the first transistor has a first gate structure having a first height and the second transistor has a second gate structure having a second height such that, in fabrication, the first gate structure and second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant.

6 . The electronic device of claim 5 , wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region.

7 . The electronic device of claim 1 , wherein the first transistor has a threshold voltage matched to a threshold voltage of the second transistor.

8 . A system comprising:
a memory device having a memory cell array coupled to a sense amplifier, the sense amplifier having:
a first transistor including a first drain region and a source region; and
a second transistor including the source region and a second drain region, the source region having a source junction depth shallower than a first drain junction depth of the first drain region and shallower than a second drain junction depth of the second drain region.

9 . The system of claim 8 , wherein the first drain junction depth is at least twice the source junction depth.

10 . The system of claim 8 , wherein the first transistor has a first gate structure having a first height and the second transistor has a second gate structure having a second height such that, in fabrication, the first gate structure and the second gate structure block doping of the source region during additional doping of the first and second drain regions using a tilted implant.

11 . The system of claim 10 , wherein a tilt angle of the tilted implant is a function of a distance between the first gate structure and the second gate structure over the source region.

12 . The system of claim 8 , wherein the sense amplifier is a p-type sense amplifier.

13 . A method of forming an electronic device, the method comprising:
forming a first transistor including a first drain region and a source region in a substrate; and forming a second transistor in the substrate, the second transistor including the source region and a second drain region, the source region having a source junction depth shallower than a first drain junction depth of the first drain region and shallower than a second drain junction depth of the second drain region.

14 . The method of claim 13 , wherein the method includes forming the source region and portions of the first drain region and portions of the second drain region prior to forming the first drain region to the first drain junction depth and prior to forming the second drain region to the second drain junction depth.

15 . The method of claim 13 , wherein the method includes:
forming a first gate structure of the first transistor on a first dielectric, the first dielectric extending between the source region and the first drain region; forming a second gate structure of the second transistor on a second dielectric, the second dielectric extending between the source region and the second drain region; and implanting additional dopants into the first drain region and additional dopants into the second drain region at a tilt angle such that the first gate structure and the second gate structure block implanting additional dopants into the source region.

16 . The method of claim 15 , wherein the tilt angle is a function of a distance between the first gate structure and the second gate structure.

17 . The method of claim 15 , wherein the tilt angle is in a range from about twenty-five degrees to about fifty degrees.

18 . The method of claim 13 , wherein the method includes forming the first transistor having a threshold voltage matched to a threshold voltage of the second transistor.

19 . The method of claim 13 , wherein the method includes:
forming a first gate structure for the first transistor, the first gate structure having a first height; forming a second gate structure for the second transistor, the second gate structure having a second height; and doping the first drain region and the second drain region with additional doping, with the first gate structure and the second gate structure blocking doping of the source region during the doping of the first drain region and the second drain region with additional doping.

20 . The method of claim 13 , wherein the method includes forming the second drain junction depth being at least twice the source junction depth.

Assignees

• Micron Technology Inc

Inventors

• Pulugurtha Srinivas
• Mocuta Dan Mihai

Classifications

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title