Layer stacks for a resistive memory element

Patent metadata

Field	Value
Publication number	US-2024268241-A1
Application number	US-202318105922-A
Country	US
Kind code	A1
Filing date	Feb 6, 2023
Priority date	Feb 6, 2023
Publication date	Aug 8, 2024
Grant date	—

Abstract

Structures that include a layer stack for a resistive memory element and methods of forming a structure that includes a layer stack for a resistive memory element. The structure comprises a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode. The first electrode includes a first layer and a second layer between the first layer and the switching layer. The switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer.

First claim

What is claimed is:

1 . A structure for a random-access resistive memory device, the structure comprising:
a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode, the first electrode including a first layer and a second layer between the first layer and the switching layer, the switching layer having a first thickness, and the second layer of the first electrode having a second thickness that is less than the first thickness of the switching layer.

2 . The structure of claim 1 further comprising:
an interconnect structure including a dielectric layer and a metal feature in the dielectric layer,
wherein the first electrode is disposed on the metal feature.

3 . The structure of claim 2 wherein the dielectric layer comprises silicon dioxide, and the metal feature comprises tantalum nitride.

4 . The structure of claim 3 wherein the first layer of the first electrode comprises tantalum nitride.

5 . The structure of claim 2 wherein the first layer of the first electrode adjoins the metal feature, and the second layer of the first electrode adjoins the switching layer.

6 . The structure of claim 2 wherein the metal feature has a trapezoidal shape with a first width that increases with decreasing distance from the first layer of the first electrode, and the first layer of the first electrode has a second width that is greater than the first width.

7 . The structure of claim 1 wherein the first layer of the first electrode comprises a first material, and the second layer of the first electrode comprises a second material with a different composition from the first material.

8 . The structure of claim 7 wherein the first material is tantalum nitride, and the second material is titanium.

9 . The structure of claim 1 further comprising:
a field-effect transistor including a drain coupled to the first layer of the first electrode.

10 . The structure of claim 1 further comprising:
a capping layer extending across the resistive memory element, the capping layer comprising silicon nitride.

11 . The structure of claim 1 wherein the second electrode includes a first layer and a second layer between the first layer and the switching layer.

12 . The structure of claim 11 wherein the first layer comprises tantalum nitride, and the second layer comprises platinum.

13 . The structure of claim 11 wherein the first layer of the second electrode is disposed on a first portion of the second layer of the second electrode, and further comprising:
a plurality of spacers disposed on respective second portions of the second layer of the second electrode.

14 . The structure of claim 13 wherein the first layer of the second electrode comprises a metal nitride, and the plurality of spacers of the second electrode comprise the metal nitride and oxygen.

15 . The structure of claim 13 wherein the first layer of the second electrode comprises tantalum nitride, and the plurality of spacers comprise tantalum oxynitride.

16 . The structure of claim 1 wherein the second thickness of the second layer of the first electrode is in a range of about 3 nanometers to about 5 nanometers.

17 . A method of forming a structure for a random-access resistive memory device, the method comprising:
forming a resistive memory element including a first electrode, a second electrode, and a switching layer disposed between the second electrode and the first electrode, wherein the first electrode includes a first layer and a second layer between the first layer and the switching layer, the switching layer has a first thickness, and the second layer of the first electrode has a second thickness that is less than the first thickness of the switching layer.

18 . The method of claim 17 wherein forming the resistive memory element including the first electrode, the second electrode, and the switching layer between the second electrode and the first electrode comprises:
depositing a layer stack including a layer; and
patterning the layer with a reactive ion etching process to form a portion of the second electrode and a plurality of spacers adjacent to the portion of the second electrode.

19 . The method of claim 18 wherein the reactive ion etching process is performed using a gas mixture that contains argon and oxygen.

20 . The method of claim 19 wherein a ratio of argon to oxygen in the gas mixture ranges from 12:0.8 to 12:1.2.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Hsieh Curtis Chun-I
• Kang Kai
• Yi Wanbing
• Sun Yongshun
• Toh Eng-Huat
• Tan Juan Boon

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B63/30

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10B63/00

  Resistance change memory devices, e.g. resistive RAM [ReRAM] devices · CPC title

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title

• H10N70/20

  Multistable switching devices, e.g. memristors · CPC title