Thermal Enhanced Power Semiconductor Package

Patent metadata

Field	Value
Publication number	US-2024243031-A1
Application number	US-202318154353-A
Country	US
Kind code	A1
Filing date	Jan 13, 2023
Priority date	Jan 13, 2023
Publication date	Jul 18, 2024
Grant date	—

Abstract

Power semiconductor packages are provided. In one example, a power semiconductor package may include a first carrier substrate. The first carrier substrate may include one or more conductive pads. The power semiconductor package may include a second carrier substrate. The second carrier substrate may include one or more conductive leads. The power semiconductor package may include a power semiconductor die having a first surface and an opposing second surface. The first surface of the power semiconductor die may be directly coupled to the first carrier substrate. The second surface of the power semiconductor die may be directly coupled to the second carrier substrate.

First claim

1 . A power semiconductor package, comprising:
a first carrier substrate, the first carrier substrate comprising one or more conductive pads; a second carrier substrate, the second carrier substrate comprising one or more conductive leads; and a power semiconductor die having a first surface and an opposing second surface; wherein the first surface of the power semiconductor die is directly coupled to the first carrier substrate; wherein the second surface of the power semiconductor die is directly coupled to the second carrier substrate.

2 . The power semiconductor package of claim 1 , wherein the power semiconductor die comprises a first contact on the first surface and a second contact on the second surface, wherein the first contact is directly coupled to at least one of the one or more conductive pads of the first carrier substrate, wherein the second contact is directly coupled to the second carrier substrate.

3 . (canceled)

4 . The power semiconductor package of claim 23 , wherein the power semiconductor die comprises a third contact on the first surface, wherein the one or more conductive pads of the first carrier substrate comprises a first conductive pad and a second conductive pad, wherein the first contact is directly coupled to the first conductive pad and the third contact is directly coupled to the second conductive pad.

5 . (canceled)

6 . The power semiconductor package of claim 1 , wherein the first carrier substrate is coupled to one or more second conductive leads of the power semiconductor package.

7 . The power semiconductor package of claim 1 , wherein the power semiconductor die is directly coupled to the first carrier substrate in a flip chip configuration.

8 . The power semiconductor package of claim 1 , wherein the first carrier substrate comprises a direct bonded copper (DBC) substrate or an active metal brazed (AMB) substrate.

9 . The power semiconductor package of claim 1 , wherein the second carrier substrate comprises a lead frame for the power semiconductor package.

10 . The power semiconductor package of claim 1 , wherein the first carrier substrate comprises a first surface and an opposing second surface, wherein the one or more conductive pads are on the first surface of the first carrier substrate, wherein the first carrier substrate comprises a thermally conductive cooling layer on the second surface.

11 . The power semiconductor package of claim 10 , wherein the thermally conductive cooling layer is exposed through an encapsulating portion of the power semiconductor package.

12 . The power semiconductor package of claim 10 , wherein the thermally conductive cooling layer is covered by an encapsulating portion of the power semiconductor package.

13 . The power semiconductor package of claim 1 , further comprising an insulating layer on the first contact of the power semiconductor die, wherein the insulating layer comprises a first dielectric material.

14 . (canceled)

15 . The power semiconductor package of claim 13 , further comprising an encapsulating portion, the encapsulating portion comprising a second dielectric material.

16 . The power semiconductor package of claim 15 , wherein the first dielectric material is different from the second dielectric material such that the first dielectric material has a first dielectric constant, and the second dielectric material has a second dielectric constant, the first dielectric constant being different from the second dielectric constant.

17 . (canceled)

18 . The power semiconductor package of claim 15 , wherein the first dielectric material is the same as the second dielectric material.

19 . (canceled)

20 . The power semiconductor package of claim 1 , wherein the power semiconductor die comprises a wide band gap semiconductor.

21 . The power semiconductor package of claim 20 , wherein the wide band gap semiconductor is silicon carbide.

22 . The power semiconductor package of claim 1 , wherein the power semiconductor package does not include any wire bonds to the power semiconductor die.

23 . The power semiconductor package of claim 1 , wherein the power semiconductor die comprises a silicon carbide-based MOSFET.

24 . The power semiconductor package of claim 1 , wherein the power semiconductor die comprises a silicon carbide-based Schottky diode.

25 .- 41 . (canceled)

42 . A method of fabricating a power semiconductor package, the method comprising:
directly coupling a power semiconductor die to a first carrier substrate to form a first assembly; directly coupling the first assembly to a second carrier substrate, the second carrier substrate comprising one or more conductive leads; and encapsulating at least a portion of the first carrier substrate, the second carrier substrate, and the power semiconductor die to form an encapsulating portion.

43 .- 58 . (canceled)

Assignees

• Wolfspeed Inc

Inventors

• Lin Yusheng
• Saxena Kuldeep
• Balaraman Devarajan

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W40/255 Primary

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D8/60 Primary

  Schottky-barrier diodes · CPC title