Analog-to-digital converter system using reference analog-to-digital converter with sampling point shifting and associated calibration method

Patent metadata

Field	Value
Publication number	US-2022131549-A1
Application number	US-202117381212-A
Country	US
Kind code	A1
Filing date	Jul 21, 2021
Priority date	Oct 28, 2020
Publication date	Apr 28, 2022
Grant date	—

Abstract

An analog-to-digital converter (ADC) system includes a main ADC, a reference ADC, a sampling control circuit, and a calibration circuit. The main ADC obtains a first sampled input voltage by sampling an analog input according to a first sampling clock, and performs analog-to-digital conversion upon the first sampled voltage to generate a first sample value. The reference ADC obtains a second sampled voltage by sampling the analog input according to a second sampling clock, and performs analog-to-digital conversion upon the second sampled voltage to generate a second sample value. The sampling control circuit controls the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases, and adjusts the second sample value to generate a reference sample value. The calibration circuit applies calibration to the main ADC according to the first sample value and the reference sample value.

First claim

What is claimed is:

1 . An analog-to-digital converter (ADC) system, comprising:
a main ADC, arranged to obtain a first sampled input voltage by sampling an analog input according to a first sampling clock, and perform analog-to-digital conversion upon the first sampled voltage to generate a first sample value; a reference ADC, arranged to obtain a second sampled voltage by sampling the analog input according to a second sampling clock, and perform analog-to-digital conversion upon the second sampled voltage to generate a second sample value; a sampling control circuit, arranged to control the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases, and further arranged to adjust the second sample value to generate a reference sample value; and a calibration circuit, arranged to apply calibration to the main ADC according to the first sample value and the reference sample value.

2 . The ADC system of claim 1 , wherein the sampling control circuit is arranged to generate the second sampling clock according to a reference clock, and the reference clock and the second sampling clock have a same frequency but different phases.

3 . The ADC system of claim 2 , wherein the sampling control circuit comprises:
a delay circuit, arranged to generate the second sampling clock by applying a delay amount to the reference clock for sampling point shifting.

4 . The ADC system of claim 3 , wherein the delay amount is a fixed value.

5 . The ADC system of claim 3 , wherein the sampling control circuit further comprises:
a compensation circuit, arranged to determine a compensation value, and generate the reference sample value by combining the compensation value and the second sample value to compensate for a sample value offset resulting from the sampling point shifting.

6 . The ADC system of claim 1 , wherein the calibration circuit comprises:
a subtractor circuit, arranged to calculate an error between the first sample value and the reference sample value; a skew estimation circuit, arranged to estimate a timing skew according to the error, and generate a first control signal and a second control signal according to the timing skew; a first skew correction circuit, arranged to adjust a phase of the first sampling clock according to the first control signal; and a second skew correction circuit, arranged to adjust a digital output of the main ADC according to the second control signal.

7 . The ADC system of claim 6 , wherein the first skew correction circuit comprises:
a digitally controlled delay line, arranged to generate the first sampling clock by applying an adjustable delay amount to a reference clock, where the adjustable delay amount is set by the first control signal.

8 . The ADC system of claim 1 , wherein the ADC system comprises a plurality of main ADCs, the main ADC is any of the plurality of main ADCs, and the reference ADC is used to calibrate all of the plurality of main ADCs.

9 . The ADC system of claim 8 , wherein the ADC system comprises a time-interleaved ADC using the plurality of main ADCs.

10 . An analog-to-digital converter (ADC) calibration method, comprising:
performing, by a main ADC, analog-to-digital conversion upon a first sampled voltage to generate a first sample value, wherein the first sampled input voltage is obtained by sampling an analog input according to a first sampling clock of the main ADC; performing, by a reference ADC, analog-to-digital conversion upon a second sampled voltage to generate a second sample value, wherein the second sampled voltage is obtained by sampling the analog input according to a second sampling clock of the reference ADC; controlling the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases; adjusting the second sample value to generate a reference sample value; and applying calibration to the main ADC according to the first sample value and the reference sample value.

11 . The ADC calibration method of claim 10 , wherein controlling the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases comprises:
generating the second sampling clock according to a reference clock, wherein the reference clock and the second sampling clock have a same frequency but different phases.

12 . The ADC calibration method of claim 11 , wherein generating the second sampling clock according to the reference clock comprises:
generating the second sampling clock by applying a delay amount to the reference clock for sampling point shifting.

13 . The ADC calibration method of claim 12 , wherein the delay amount is a fixed value.

14 . The ADC calibration method of claim 12 , wherein adjusting the second sample value to generate the reference sample value comprises:
determining a compensation value; and generating the reference sample value by combining the compensation value and the second sample value to compensate for a sample value offset resulting from the sampling point shifting.

15 . The ADC calibration method of claim 10 , wherein applying calibration to the main ADC according to the first sample value and the reference sample value comprises:
calculating an error between the first sample value and the reference sample value; estimating a timing skew according to the error; generating a first control signal and a second control signal according to the timing skew; adjusting a phase of the first sampling clock according to the first control signal; and adjusting a digital output of the main ADC according to the second control signal.

16 . The ADC calibration method of claim 15 , wherein adjusting the phase of the first sampling clock according to the first control signal comprises:
applying, by a digitally controlled delay line, an adjustable delay amount to a reference clock for generating the first sampling clock, wherein the adjustable delay amount is set by the first control signal.

17 . The ADC calibration method of claim 10 , wherein the main ADC is any of a plurality of main ADCs, and the reference ADC is used to calibrate all of the plurality of main ADCs.

18 . The ADC calibration method of claim 17 , wherein the plurality of main ADCs are included in a time-interleaved ADC.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Huang Sheng-Jui

Classifications

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/1061 Primary

  using digitally programmable trimming circuits · CPC title

• H03M1/1215

  using time-division multiplexing · CPC title

• H03M1/0863

  of switching transients, e.g. glitches · CPC title

• H03M1/0624

  by synchronisation · CPC title