Time-efficient offset cancellation for multi-stage converters

Patent metadata

Field	Value
Publication number	US-10868554-B1
Application number	US-201916706230-A
Country	US
Kind code	B1
Filing date	Dec 6, 2019
Priority date	Dec 6, 2019
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

Techniques to reduce the on-time of a multi-stage ADC circuit by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. The techniques can allow the signal conditioning circuit and the residue amplifier to settle together.

First claim

The claimed invention is:

1. A method of canceling an offset of a signal conditioning circuit coupled to an input of a multi-stage analog-to-digital converter (ADC) circuit, the method comprising:
sampling an analog input signal and the offset;
performing; by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset;
canceling the offset and amplifying a residue of the sampled analog input signal;
performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal; and
generating a digital output signal representing the sampled analog input signal.

2. The method of claim 1 , wherein canceling the offset comprises:
shorting an input of the signal conditioning circuit to determine the offset; and
subtracting the offset from the sampled analog input signal and offset.

3. The method of claim 1 , wherein performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes:
performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset using a successive approximation register (SAR) algorithm.

4. The method of claim 1 , wherein performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes:
performing; by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset using a delta-sigma algorithm.

5. The method of claim 1 , wherein performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes:
performing; by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset using a flash converter.

6. The method of claim 1 , wherein performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input includes:
performing; by the second stage of the ADC circuit; the second conversion on the residue of the sampled analog input using a successive approximation register (SAR) algorithm.

7. The method of claim 1 , wherein performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input includes:
performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input using a delta-sigma algorithm.

8. The method of claim 1 , wherein performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input includes:
performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input using a flash converter.

9. A multi-stage analog-to-digital converter (ADC) circuit having an input coupled to a signal conditioning circuit having an offset, the ADC circuit comprising:
a sample-and-hold circuit that samples an analog input signal and the offset;
a first stage including a first ADC sub-circuit that performs a first conversion on the sampled analog input signal and offset;
a control circuit that operates a plurality of switches to generate the residue of the first conversion and eliminate the signal conditioning circuit offset from the residue;
a residue amplifier that amplifies the residue of the sampled analog input signal;
a second stage including a second ADC sub-circuit that performs a second conversion on the residue of the sampled analog input signal; and
an encoder circuit that combines first and second conversion results and generate a digital output signal representing the sampled analog input signal.

10. The circuit of claim 9 , wherein the first ADC sub-circuit includes a successive approximation register (SAR) ADC configured to perform a SAR algorithm.

11. The circuit of claim 9 , wherein the first ADC sub-circuit includes a delta-sigma ADC that performs a delta-sigma algorithm.

12. The circuit of claim 9 , wherein the first ADC sub-circuit includes a flash ADC that performs a flash algorithm.

13. The circuit of claim 9 , wherein the second ADC sub-circuit includes a successive approximation register (SAR) ADC that performs a SAR algorithm.

14. The circuit of claim 9 , wherein the second ADC sub-circuit includes a delta-sigma ADC that performs a delta-sigma algorithm.

15. The circuit of claim 9 , wherein the second ADC sub-circuit includes a flash ADC configured that performs a flash algorithm.

16. The circuit of claim 9 , wherein the first ADC sub-circuit and/or the second ADC sub-circuit is a hybrid ADC circuit that performs at least two algorithms selected from a group consisting of a successive approximation register (SAR) algorithm, a delta-sigma algorithm, and a flash algorithm.

17. The circuit of claim 9 , wherein the signal conditioning circuit is a buffer circuit.

18. A multi-stage analog-to-digital converter (ADC) circuit having an input coupled to a signal conditioning circuit having an offset, the ADC circuit comprising:
a sample-and-hold circuit configured to sample an analog input signal and the offset;
means for performing, by a first stage of the ADC circuit, a first conversion on the sampled analog input signal and offset;
means for canceling the offset and amplifying a residue of the sampled analog input signal;
means for performing, by a second stage of the ADC circuit, a second conversion on the residue of the sampled analog input signal; and
means for generating a digital output signal representing the sampled analog input signal.

19. The circuit of claim 18 , wherein the means for performing, by the first stage of the ADC circuit, the first conversion on the sampled analog input signal and offset includes a successive approximation register (SAR) ADC configured to perform a SAR algorithm.

20. The circuit of claim 18 , wherein the means for performing, by the second stage of the ADC circuit, the second conversion on the residue of the sampled analog input signal includes a successive approximation register (SAR) ADC configured to perform a SAR algorithm.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Reitsma George Pieter
• Perry Raymond Thomas

Classifications

• H03M1/129 Primary

  Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M1/18 takes precedence); Out-of-range indication · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/167

  all stages comprising simultaneous converters (H03M1/165 takes precedence) · CPC title

• H03M3/356

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M3/494) · CPC title