Ferroelectric capacitor within backside interconnect

Patent metadata

Field	Value
Publication number	US-2024114694-A1
Application number	US-202217937043-A
Country	US
Kind code	A1
Filing date	Sep 30, 2022
Priority date	Sep 30, 2022
Publication date	Apr 4, 2024
Grant date	—

Abstract

Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a device layer including a transistor; a frontside interconnect structure above the device layer and having a conductive interconnect feature connected to a first terminal of the transistor; and a backside interconnect structure below the device layer and having a ferroelectric capacitor connected to a second terminal of the transistor.

2 . The integrated circuit of claim 1 , wherein the backside interconnect structure includes first and second interconnect layers, with a first etch stop between the device layer and the first interconnect layer, and a second etch stop at least partially between the first and second interconnect layers, and the ferroelectric capacitor has a height equal to or greater than the vertical distance between the first and second etch stops.

3 . The integrated circuit of claim 1 , wherein the ferroelectric capacitor comprises:
an inner electrode connected to an interconnect feature in an interconnect layer below the ferroelectric capacitor; an outer electrode connected to the second terminal of the transistor; and a layer of ferroelectric material between the inner and outer electrodes.

4 . The integrated circuit of claim 1 , wherein the ferroelectric capacitor comprises:
an inner electrode connected to the second terminal of the transistor; an outer electrode connected to an interconnect feature in an interconnect layer that is below the ferroelectric capacitor or includes at least part of the ferroelectric capacitor; and a layer of ferroelectric material between the inner and outer electrodes.

5 . The integrated circuit of claim 4 , wherein the ferroelectric capacitor is a multi-plate capacitor in which the outer conductor is one of a plurality of plate line conductors arranged in a staircase structure.

6 . The integrated circuit of claim 4 , wherein the backside interconnect structure includes first and second interconnect layers, with a first etch stop between the device layer and the first interconnect layer, a second etch stop at least partially between the first and second interconnect layers, and a third etch stop below the second interconnect layer, and the ferroelectric capacitor has a height greater than the vertical distance between the first and second etch stops and up to the vertical distance between the first and third etch stops.

7 . The integrated circuit of claim 1 , wherein the transistor comprises:
a body of semiconductor material extending from a source region to a drain region; a gate structure over the semiconductor material between the source and drain regions; a contact on a bottom surface of the source or drain region; and wherein an electrode of the ferroelectric capacitor is coupled to the source or drain region by the contact.

8 . The integrated circuit of claim 1 , wherein the second terminal of the transistor includes a backside contact that is below and in contact with a source or drain region of the transistor, and an electrode of the ferroelectric capacitor is in contact with the backside contact.

9 . The integrated circuit of claim 8 , wherein the backside contact is self-aligned with the source or drain region which it is below.

10 . A integrated circuit memory cell, comprising:
an access transistor including a body of semiconductor material extending from a source region to a drain region, and a backside contact extending downward from a bottom surface of the source or drain region; and a capacitor including a layer of ferroelectric material between first and second electrodes, the backside contact on the first electrode, and the second electrode in contact with a backside interconnect feature.

11 . The integrated circuit memory cell of claim 10 , wherein the capacitor has a height that extends at least one interconnect layer.

12 . The integrated circuit of memory cell claim 10 , wherein the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors configured in a staircase structure.

13 . The integrated circuit memory cell of claim 10 , wherein the backside contact is self-aligned with the source or drain region which it is below.

14 . The integrated circuit memory cell of claim 10 , wherein the layer of ferroelectric material is configured to isolate the backside interconnect feature from the first electrode.

15 . The integrated circuit memory cell of claim 10 , wherein the layer of ferroelectric material extends between the backside interconnect feature and the first electrode.

16 . A integrated circuit capacitor structure, comprising:
a first electrode connected to a transistor terminal by a backside contact, the backside contact extending downward from a bottom surface of the transistor terminal to the first electrode; a second electrode connected to an interconnect feature in an interconnect layer that is below the capacitor or includes at least part of the capacitor; and a layer of ferroelectric material between the first and second electrodes.

17 . The integrated circuit capacitor structure of claim 16 , wherein the first electrode includes a layer of conductive material on a bottom surface of the backside contact and sidewalls of a trench extending downward from the backside contact, and the layer of ferroelectric material is on the layer of conductive material, and the second electrode includes a body of conductive material on the layer of ferroelectric material.

18 . The integrated circuit capacitor structure of claim 16 , wherein the first electrode includes a body of conductive material extending downward from the backside contact, and the layer of ferroelectric material is on sidewalls of the first electrode, and the second electrode extends laterally outward from the layer of ferroelectric material, wherein the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure.

19 . The integrated circuit capacitor structure of claim 16 , wherein the capacitor has a height that extends through at least one interconnect layer.

20 . The integrated circuit capacitor structure of claim 16 , wherein the transistor terminal is a source or drain region, and the backside contact is self-aligned with the source or drain region.

Assignees

• Intel Corp

Inventors

• Dutta Sourav
• Haratipour Nazila
• Avci Uygar E
• Kumar Vachan
• Neumann Christopher M
• Shivaraman Shriram
• Chang Sou-Chi
• Doyle Brian S

Classifications

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• H01L27/11507 Primary

  Electricity · mapped topic

• H10B53/30 Primary

  characterised by the memory core region · CPC title