SRAM memory having subarrays with common IO block

Patent metadata

Field	Value
Publication number	US-10867681-B2
Application number	US-201916240175-A
Country	US
Kind code	B2
Filing date	Jan 4, 2019
Priority date	Mar 23, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.

First claim

What is claimed is:

1. A memory device, comprising:
an array of SRAM memory cells, the array including a first sub array and a second sub array;
a first plurality of bit lines connected to the memory cells of the first sub array;
a second plurality of bit lines connected to the memory cells of the second sub array;
an IO block situated between the first sub array and the second sub array, wherein the first plurality of bit lines extend from the first sub array directly to the IO block, the second plurality of bit lines extend from the second sub array directly to the IO block and wherein the IO block includes data input and output terminals configured to receive data to be written to the first and second arrays and output data read from the first and second arrays the first plurality of bit lines and the second plurality of bit lines.

2. The memory device of claim 1 , wherein the IO block includes an output latch coupled to receive data read from the first plurality of bit lines and the second plurality of bit lines.

3. The memory device of claim 1 , wherein:
the memory cells of the first and second sub arrays are arranged in columns and rows;
the bit lines extend parallel to the columns; and
the IO block is situated across the columns, perpendicular to the bit lines.

4. The memory device of claim 2 , further comprising:
a plurality of word lines connected to the memory cells and extending parallel to the rows; and
a row decoder connected to the plurality of word lines.

5. The memory device of claim 4 , wherein the array further includes a third sub array and a fourth sub array, wherein the first sub array and third sub array are positioned on a first side of the IO block and the second sub array and the fourth sub array are positioned on a second side of the IO block opposite the first side, and wherein the first sub array and the second sub array are positioned on a first side of the row decoder and the third sub array and the fourth sub array are positioned on a second side of the row decoder.

6. The memory device of claim 2 , wherein the IO block includes:
a first sense amplifier coupled to receive data from the first plurality of bit lines and not the second plurality of bit lines, and provide a first output to the output latch; and
a second sense amplifier coupled to receive data from the second plurality of bit lines and not the first plurality of bit lines, and provide a second output to the output latch.

7. The memory device of claim 6 , wherein the IO block includes
a first read multiplexer coupled to receive data from the first plurality of bit lines and provide a first output to the first sense amplifier; and
a second read multiplexer coupled to receive data from the second plurality of bit lines and provide a second output to the second sense amplifier.

8. The memory device of claim 7 , wherein the IO block includes a write controller coupled to the first plurality of bit lines and the second plurality of bit lines.

9. The memory device of claim 6 , wherein the first and second sense amplifiers are configured to receive respective first and second enable signals.

10. The memory device of claim 9 , wherein the first and second sense amplifiers are configured with tri-state logic.

11. A memory input/output (TO), comprising:
a first side and a second side opposite the first side, the first side configured to receive a first plurality of bit lines from a first memory sub array having a plurality of SRAM cells, the second side configured to receive a second plurality of bit lines from a second memory sub array having a plurality of SRAM cells;
a first read multiplexer coupled to receive data from the first plurality of bit lines, and configured provide a first output in response to a first column select signal;
a second read multiplexer coupled to receive data from the second plurality of bit lines, and configured provide a second output in response to a second column select signal;
an output latch coupled to receive the first and second outputs from the first and second read multiplexers; and
a data output terminal configured to provide an output from the output latch.

12. The memory IO of claim 11 , wherein the memory IO is situated between the first and second sub arrays.

13. The memory IO of claim 11 , wherein the SRAM memory cells of the first and second sub arrays are arranged in columns and rows with the bit lines extending parallel to the columns, and wherein the memory IO is situated across the columns perpendicular to the bit lines.

14. The memory IO of claim 11 , further comprising a write controller configured to receive data from a data input terminal and configured to write the data to the first and second plurality of bit lines.

15. The memory IO of claim 11 , further comprising:
a first sense amplifier coupled to receive the first output from the first read multiplexer and provide the first output to the output latch; and
a second sense amplifier coupled to receive the second output from the second read multiplexer and provide the second output to the output latch.

16. A memory input/output (TO) method, comprising:
providing an array of SRAM memory cells;
positioning an IO block so as to divide the array of SRAM memory cells into a first sub array and a second sub array situated on opposite sides of the IO block;
receiving a first plurality of bit lines connected to the SRAM memory cells of the first sub array at a first side of the IO block;
receiving a second plurality of bit lines connected to the SRAM memory cells of the second sub array at a second side of the IO block;
operating the IO block to receive data from the SRAM memory cells of the first sub array by a first read multiplexer;
operating the IO block to output data from the first read multiplexer to a first sense amplifier in response to a first column select signal;
operating the IO block to output data from the first sense amplifier to an output latch in response to a first sense amplifier enable signal;
operating the IO block to receive data from the SRAM memory cells of the second sub array by a second read multiplexer;
operating the IO block to output data from the second read multiplexer to a second sense amplifier in response to a second column select signal; and
operating the IO block to output data from the second sense amplifier to the output latch in response to a second sense amplifier enable signal.

17. The method of claim 16 , further comprising operating the IO block to write data to the memory cells of the first and second sub arrays.

18. The method of claim 16 , wherein the memory cells of the first and second sub arrays are arranged in columns and rows, and wherein the bit lines extend parallel to the columns, and wherein the method further comprises the situating the TO block across the columns, perpendicular to the bit lines.

19. The method of claim 18 , further comprising situating a row decoder parallel to the word lines so as to form a third sub array and a fourth sub array on opposite sides of the row decoder.

20. The method of claim 16 , wherein positioning the IO block so as to divide the array of memory cells into the first sub array and the second sub array includes positioning first and second IO blocks that include the IO block so as to divide the array of memory cells into the first sub array and the second sub array.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Clinton Michael
• Sheffield Bryan David
• Tsai Marty
• Singh Rajinder

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• H10B10/00

  Static random access memory [SRAM] devices · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title