Etching composition and method of manufacturing integrated circuits using the same

Patent metadata

Field	Value
Publication number	US-2024059967-A1
Application number	US-202318227454-A
Country	US
Kind code	A1
Filing date	Jul 28, 2023
Priority date	Aug 18, 2022
Publication date	Feb 22, 2024
Grant date	—

Abstract

An etching composition for etching a titanium aluminum nitride layer and a method of manufacturing an integrated circuit, the etching composition includes about 15 wt % to about 30 wt % of an oxidizing agent; about 1 wt % to about 10 wt % of a pH adjusting agent, the pH adjusting agent including an inorganic acid or an organic acid; about 0.001 wt % to about 1 wt % of an etching booster; and a solvent, all wt % being based on a total weight of the etching composition.

First claim

What is claimed is:

1 . An etching composition for etching a titanium aluminum nitride layer, the etching composition comprising:
about 15 wt % to about 30 wt % of an oxidizing agent; about 1 wt % to about 10 wt % of a pH adjusting agent, the pH adjusting agent including an inorganic acid or an organic acid; about 0.001 wt % to about 1 wt % of an etching booster; and a solvent, all wt % being based on a total weight of the etching composition.

2 . The etching composition as claimed in claim 1 , wherein the etching composition has a pH that is greater than 0 and less than or equal to 3.

3 . The etching composition as claimed in claim 1 , wherein the oxidizing agent includes hydrogen peroxide.

4 . The etching composition as claimed in claim 1 , wherein the pH adjusting agent includes phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, acetic acid, methanesulfonic acid, ethanesulfonic acid, benzenesulfonic acid, sulfamic acid, sulfanilic acid, malonic acid, glycolic acid, formic acid, citric acid, oxalic acid, propionic acid, acrylic acid, lactic acid, or butyric acid.

5 . The etching composition as claimed in claim 1 , wherein the etching booster includes monoammonium phosphate, diammonium phosphate, ammonium triphosphate, ammonium sulfate, ammonium bisulfate, ammonium persulfate, ammonium chloride, ammonium nitrite, ammonium fluoride, methyl methanesulfonate, ethanesulfonate, benzenesulfonate, ammonium sulfamate, ethylenediaminetetraacetic acid, iminodiacetic acid, diethylenetriaminepentaacetic acid, aminotrismethylenephosphonic acid, phosphorous acid, glycine, phenylphosphonic acid, sulfamic acid nitrotrismethylenephosphonic acid, 1-hydroxyethene-1,1-diphosphonic acid, dopamine, or adrenaline.

6 . The etching composition as claimed in claim 1 , wherein:
the etching composition has a first etching rate for titanium aluminum nitride under a predetermined etching condition, and the etching composition has a second etching rate for a hafnium oxide, a zirconium oxide, or an aluminum oxide under the predetermined etching condition, the second etching rate being less than the first etching rate.

7 . A method of manufacturing an integrated circuit, the method comprising:
forming a semiconductor pattern on a substrate; forming a gate insulating layer on the semiconductor pattern; forming a titanium aluminum nitride layer on the gate insulating layer; and performing an etching process using a composition on the titanium aluminum nitride layer to remove the titanium aluminum nitride layer, wherein the composition includes the etching composition of claim 1 .

8 . The method as claimed in claim 7 , wherein the gate insulating layer is not removed and remains after the etching process.

9 . The method as claimed in claim 8 , wherein the gate insulating layer includes a metal oxide, the metal oxide including a hafnium oxide, a zirconium oxide, or an aluminum oxide.

10 . The method as claimed in claim 9 , wherein:
the composition has a first etching rate for a titanium aluminum nitride under a predetermined etching condition, and the composition has a second etching rate for the metal oxide under the predetermined etching condition, the second etching rate being less than the first etching rate.

11 . The method as claimed in claim 7 , wherein:
the composition has a pH that is greater than 0 and less than or equal to 3, and the oxidizing agent includes hydrogen peroxide.

12 . The method as claimed in claim 7 , wherein the pH adjusting agent includes phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, acetic acid, methanesulfonic acid, ethanesulfonic acid, benzenesulfonic acid, sulfamic acid, sulfanilic acid, malonic acid, glycolic acid, formic acid, citric acid, oxalic acid, propionic acid, acrylic acid, lactic acid, or butyric acid.

13 . A method of manufacturing an integrated circuit, the method comprising:
forming a first semiconductor pattern structure on a first region of a substrate such that the first semiconductor pattern structure includes a plurality of first semiconductor patterns separated from each other; forming a second semiconductor pattern structure on a second region of the substrate such that the second semiconductor pattern structure includes a plurality of second semiconductor patterns separated from each other; forming a gate insulating layer on the first semiconductor pattern structure and the second semiconductor pattern structure; forming a metal-containing layer on the gate insulating layer such that the metal-containing layer includes a titanium aluminum nitride; forming a mask pattern that covers a first portion of the metal-containing layer on the first region and does not cover a second portion of the metal-containing layer on the second region; and performing an etching process using a composition on the second portion of the metal-containing layer to remove the second portion of the metal-containing layer, wherein the composition includes the etching composition of claim 1 .

14 . The method as claimed in claim 13 , wherein:
the metal-containing layer not covered by the mask pattern is removed at a first etching rate during the etching process, the gate insulating layer under the metal-containing layer is removed at a second etching rate that is less than the first etching rate during the etching process, and the mask pattern is removed at a third etching rate that is less than the first etching rate during the etching process.

15 . The method as claimed in claim 14 , wherein the second etching rate is about 0.1% to about 10% of the first etching rate.

16 . The method as claimed in claim 13 , wherein the gate insulating layer includes a metal oxide, the metal oxide including a hafnium oxide, a zirconium oxide, or an aluminum oxide.

17 . The method as claimed in claim 13 , wherein:
the composition has a pH that is greater than 0 and less than or equal to 3, and the oxidizing agent includes hydrogen peroxide.

18 . The method as claimed in claim 13 , wherein the pH adjusting agent includes phosphoric acid, nitric acid, sulfuric acid, hydrochloric acid, acetic acid, methanesulfonic acid, ethanesulfonic acid, benzenesulfonic acid, sulfamic acid, sulfanilic acid, malonic acid, glycolic acid, formic acid, citric acid, oxalic acid, propionic acid, acrylic acid, lactic acid, or butyric acid.

19 . The method as claimed in claim 13 , wherein:
the gate insulating layer surrounds each of the plurality of first semiconductor patterns and each of the plurality of second semiconductor patterns, the first portion of the metal-containing layer fills first sub-gate spaces between the plurality of first semiconductor patterns, and the second portion of the metal-containing layer fills second sub-gate spaces between the plurality of second semiconductor patterns.

20 . The method as claimed in claim 19 , wherein, after the second portion of the metal-containing layer is removed, the gate insulating layer is exposed in the second sub-gate spaces between the plurality of first semiconductor patterns.

Assignees

• Samsung Electronics Co Ltd
• Oci Co Ltd

Inventors

• Kim Daihyun
• Kwon Taesoo
• Yoo Yeonsoek
• Park Mihyun
• Bae Sangwon
• Lee Hyosan
• Jang Wook

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title