Semiconductor device package and methods of formation

Patent metadata

Field	Value
Publication number	US-2024038682-A1
Application number	US-202217814997-A
Country	US
Kind code	A1
Filing date	Jul 26, 2022
Priority date	Jul 26, 2022
Publication date	Feb 1, 2024
Grant date	—

Abstract

A laser grooving operation is performed to form a plurality of grooves in a semiconductor die prior to attaching the semiconductor die to a semiconductor device package substrate. In addition to forming a first groove through which blade sawing is to be performed to separate the semiconductor die from other semiconductor dies, a second groove may be formed between the first groove and a seal ring of the semiconductor die. The second groove is configured to contain any potential delamination that might otherwise propagate to an active region of the semiconductor die. Accordingly, the second groove and the associated laser grooving operation described herein may reduce the likelihood of delamination that might otherwise be caused by swelling and/or expansion in a molding compound formed around the semiconductor die after the semiconductor die is attached to the semiconductor device package substrate.

First claim

What is claimed is:

1 . A semiconductor die package, comprising:
a semiconductor die; an insulator layer; a connection structure between the semiconductor die and the insulator layer; and a stress relief trench between an outer edge of the semiconductor die package and a seal ring structure of the semiconductor die package,
wherein the stress relief trench extends through the insulator layer, through the connection structure, and into a portion of the semiconductor die.

2 . The semiconductor die package of claim 1 , wherein a width of the stress relief trench is included in a range of approximately 5 microns to approximately 20 microns.

3 . The semiconductor die package of claim 1 , wherein the stress relief trench is included in a scribe line region of the semiconductor die package.

4 . The semiconductor die package of claim 1 , wherein the outer edge of the semiconductor die package comprises:
a curved portion and an approximately straight portion above the curved portion,
wherein a height of the stress relief trench and a height of the curved portion of the outer edge are approximately a same height.

5 . The semiconductor die package of claim 1 , wherein a height of the stress relief trench is included in a range of approximately 15 microns to approximately 60 microns.

6 . The semiconductor die package of claim 1 , wherein, in a top-down view of the semiconductor die package, the stress relief trench surrounds a seal ring region and an active region of the semiconductor die package.

7 . The semiconductor die package of claim 6 , wherein the stress relief trench is configured to reduce a likelihood of delamination propagating from a scribe line region of the semiconductor die package into the active region through the seal ring region.

8 . A method, comprising:
forming a first semiconductor die package and a second semiconductor die package, side-by-side with the first semiconductor die package, on a wafer; forming a first groove in a scribe line region between the first semiconductor die package and the second semiconductor die package; forming a second groove in the scribe line region; forming a third groove in the scribe line region,
wherein the second groove is adjacent to a first side of the first groove that faces the first semiconductor die package,
wherein the third groove is adjacent to a second side of the first groove that faces the second semiconductor die package,
wherein a width of the first groove is greater relative to a width of the second groove, and
wherein the width of the first groove is greater relative to a width of the third groove; and
cutting through a bottom of the first groove to separate the first semiconductor die package and the second semiconductor die package.

9 . The method of claim 8 , wherein forming the second groove comprises:
forming the second groove prior to forming the first groove; and wherein forming the third groove comprises:
forming the third groove prior to forming the first groove.

10 . The method of claim 8 , wherein forming the second groove comprises:
forming the second groove after forming the first groove; and wherein forming the third groove comprises:
forming the third groove after forming the first groove.

11 . The method of claim 8 , wherein forming the second groove comprises:
forming the second groove prior to forming the first groove; and wherein forming the third groove comprises:
forming the third groove after forming the first groove.

12 . The method of claim 8 , further comprising:
mounting the first semiconductor die package to a carrier substrate; forming a plurality of through integrated fanout (InFO) vias (TIVs) of a semiconductor device package adjacent to one or more sides of the first semiconductor die package; and depositing a molding compound around the first semiconductor die package and around the plurality of TIVs,
wherein the molding compound fills in the second groove to form a stress relief trench in the first semiconductor die package.

13 . The method of claim 12 , further comprising:
performing one or more reliability tests on the semiconductor device package,
wherein the stress relief trench resists a transfer of stress, from the molding compound to the semiconductor device package, that results from swelling of the molding compound during the one or more reliability tests.

14 . The method of claim 8 , wherein forming the second groove comprises:
forming the second groove to a width that is included in a range of approximately 5 microns to approximately 20 microns.

15 . A semiconductor device package, comprising:
a semiconductor device package substrate; a plurality of interconnection structures attached to the semiconductor device package substrate and extending above the semiconductor device package substrate; a first semiconductor die package between the plurality of interconnection structures, comprising:
a stress relief trench that is included around a perimeter of the first semiconductor die package;
an encapsulation layer that surrounds the plurality of interconnection structures and the first semiconductor die package; and a second semiconductor die package above the plurality of interconnection structures, above the first semiconductor die package, and above the encapsulation layer,
wherein the second semiconductor die package is attached to the plurality of interconnection structures.

16 . The semiconductor device package of claim 15 , wherein the stress relief trench is filled with material of the encapsulation layer.

17 . The semiconductor device package of claim 15 , wherein the stress relief trench is included in a bottom surface of the first semiconductor die package that faces the semiconductor device package substrate, and extends into a portion of a height of the first semiconductor die package.

18 . The semiconductor device package of claim 17 , wherein the bottom surface of the first semiconductor die package faces away from the second semiconductor die package.

19 . The semiconductor device package of claim 15 , wherein a width of the stress relief trench is included in a range of approximately 5 microns to approximately 20 microns.

20 . The semiconductor device package of claim 19 , wherein a height of the stress relief trench is included in a range of approximately 15 microns to approximately 60 microns.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tien-Chung
• Huang Li-Hsien
• Wu Ming-Feng
• Liu Yung-Sheng
• Chen Chun-Jen
• He Jun

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title