Semiconductor package

Patent metadata

Field	Value
Publication number	US-2024014163-A1
Application number	US-202318312191-A
Country	US
Kind code	A1
Filing date	May 4, 2023
Priority date	Jul 7, 2022
Publication date	Jan 11, 2024
Grant date	—

Abstract

A semiconductor package includes a redistribution substrate having a first side and an opposite second side, a semiconductor chip on the first side of the redistribution substrate, a silicon capacitor on the second side of the redistribution substrate, a plurality of solder balls on the second side of the redistribution substrate and adjacent the silicon capacitor, and a metal pattern in the redistribution substrate and positioned between the silicon capacitor and the solder balls. The metal pattern includes a first portion extending in a first direction, and a second portion connected to the first portion and extending in a second direction different from the first direction.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a redistribution substrate comprising a first side and an opposite second side; a semiconductor chip on the first side of the redistribution substrate; a silicon capacitor on the second side of the redistribution substrate; a plurality of solder balls on the second side of the redistribution substrate and adjacent the silicon capacitor; and a metal pattern in the redistribution substrate and positioned between the silicon capacitor and the plurality of solder balls, wherein the metal pattern comprises a first portion extending in a first direction, and a second portion connected to the first portion and extending in a second direction different from the first direction.

2 . The semiconductor package of claim 1 , wherein the metal pattern has at least one of a “U” shape and a rectangular shape in plan view.

3 . The semiconductor package of claim 1 , wherein a distance from the first side of the redistribution substrate to a bottom surface of the metal pattern is smaller than a distance from the first side of the redistribution substrate to the second side of the redistribution substrate.

4 . The semiconductor package of claim 3 , wherein the distance from the bottom surface of the metal pattern to the second side of the redistribution substrate is 5 μm or less.

5 . The semiconductor package of claim 1 , further comprising:
a plurality of connection members between the silicon capacitor and the redistribution substrate; and an underfill surrounding the plurality of connection members between the silicon capacitor and the redistribution substrate, wherein the underfill does not contact the metal pattern.

6 . The semiconductor package of claim 1 , further comprising:
a plurality of connection members between the silicon capacitor and the redistribution substrate; and an underfill surrounding the plurality of connection members between the silicon capacitor and the redistribution substrate, wherein the underfill contacts a portion of the metal pattern.

7 . The semiconductor package of claim 1 , wherein the metal pattern comprises a single layer.

8 . The semiconductor package of claim 7 , wherein the metal pattern comprises copper (Cu).

9 . The semiconductor package of claim 1 , wherein a length of the first portion of the metal pattern in the first direction is greater than a length of the silicon capacitor in the first direction.

10 . The semiconductor package of claim 1 , wherein the silicon capacitor has a rectangular shape in plan view, and
the metal pattern is adjacent a side surface of the silicon capacitor.

11 . A semiconductor package comprising:
a redistribution substrate comprising a first side and an opposite second side; a semiconductor chip on the first side of the redistribution substrate; a silicon capacitor on the second side of the redistribution substrate, the silicon capacitor having a rectangular shape in plan view; an underfill between the silicon capacitor and the redistribution substrate; a plurality of solder balls on the second side of the redistribution substrate and adjacent the silicon capacitor, wherein the plurality of solder balls are not in contact with the underfill; and a metal pattern within the redistribution substrate and adjacent a side surface of the silicon capacitor, wherein the metal pattern has a “U” shape in plan view.

12 . The semiconductor package of claim 11 , wherein a distance from the first side of the redistribution substrate to a bottom surface of the metal pattern is smaller than a thickness of the redistribution substrate.

13 . The semiconductor package of claim 12 , wherein a distance from the bottom surface of the metal pattern to the second side of the redistribution substrate is 5 μm or less.

14 . The semiconductor package of claim 11 , wherein at least a part of the underfill is on at least a part of the metal pattern.

15 . The semiconductor package of claim 11 , wherein the underfill does not completely cover the metal pattern.

16 . The semiconductor package of claim 11 , wherein the metal pattern comprises a first sub-pattern, and a second sub-pattern spaced apart from the first sub-pattern, and
wherein a shape of the first sub-pattern is different from a shape of the second sub-pattern in plan view.

17 . The semiconductor package of claim 11 , wherein the metal pattern comprises a single layer comprising copper (Cu).

18 . A semiconductor package comprising:
a redistribution substrate comprising a first side and an opposite second side; a semiconductor chip on the first side of the redistribution substrate; a silicon capacitor on the second side of the redistribution substrate, wherein the silicon capacitor has a rectangular shape in plan view; a plurality of connection members between the silicon capacitor and the redistribution substrate; an underfill surrounding the plurality of connecting members between the silicon capacitor and the redistribution substrate; a plurality of solder balls on the second side of the redistribution substrate and adjacent the silicon capacitor; and a single layer metal pattern within the redistribution substrate between the silicon capacitor and the plurality of solder balls, wherein the metal pattern is adjacent a side surface of the silicon capacitor, wherein the metal pattern comprises a first portion extending in a first direction, and a second portion connected to the first portion and extending in a second direction different from the first direction, wherein a distance from the first side of the redistribution substrate to a bottom surface of the metal pattern is smaller than a distance from the first side of the redistribution substrate to the second side of the redistribution substrate, and wherein at least a part of the metal pattern contacts at least a part of the underfill.

19 . The semiconductor package of claim 18 , wherein a distance from the bottom surface of the metal pattern to the second side of the redistribution substrate is 5 μm or less.

20 . The semiconductor package of claim 18 , wherein the metal pattern has a “U” shape in plan view.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong Youn
• Kim Eung Kyu
• Bae Min Jun
• Lee Hyeon Seok
• Choi Seok Kyu

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title