Bridge interconnection with layered interconnect structures

Patent metadata

Field	Value
Publication number	US-2024014138-A1
Application number	US-202318139862-A
Country	US
Kind code	A1
Filing date	Apr 26, 2023
Priority date	May 28, 2013
Publication date	Jan 11, 2024
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . An IC assembly, comprising:
a package substrate having a cavity; a bridge disposed in the cavity of the package substrate, wherein the bridge comprises a silicon substrate; a dielectric layer over the bridge; a first interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the first interconnect piece is disposed extending in and over the dielectric layer, wherein the first interconnect piece comprises copper; a first layer on the first interconnect piece, wherein the first layer comprises nickel; a second interconnect piece disposed over the bridge and electrically coupled with the bridge, wherein the second interconnect piece is disposed extending in and over the dielectric layer, wherein the second interconnect piece comprises copper; a second layer on the second interconnect piece, wherein the second layer comprises nickel; a first interconnect structure disposed in the package substrate, wherein the first interconnect structure is laterally spaced from a first side of the bridge, wherein the first interconnect structure extends through the dielectric layer; a second interconnect structure disposed in the package substrate, wherein the second interconnect structure is laterally spaced from a second side of the bridge, wherein the second interconnect structure extends through the dielectric layer; a first die electrically coupled with the first interconnect piece and the first interconnect structure; and a second die electrically coupled with the second interconnect piece and the second interconnect structure.

2 . The IC assembly of claim 1 , wherein the first die is a processor and the second die is a memory.

3 . The IC assembly of claim 1 , wherein the first die is an application specific integrated circuit and the second die is a memory.

4 . The IC assembly of claim 1 , wherein the dielectric layer is in contact with the bridge.

5 . The IC assembly of claim 1 , wherein the first die is disposed over the bridge having a partial lateral overlap, wherein the second die is disposed over the bridge having a partial lateral overlap.

6 . The IC assembly of claim 1 , wherein the bridge is embedded in the cavity of the package substrate.

7 . The IC assembly of claim 1 , wherein the first layer and the second layer are manufacturable at the same time.

8 . An IC assembly, comprising:
a package substrate; a bridge within the package substrate, wherein the bridge comprises a silicon substrate; a dielectric layer over the bridge; a first interconnect over the bridge and electrically coupled to the bridge, wherein the first interconnect is in and over the dielectric layer, and wherein the first interconnect comprises copper; a first layer on the first interconnect, wherein the first layer comprises nickel; a second interconnect over the bridge and electrically coupled to the bridge, wherein the second interconnect is in and over the dielectric layer, and wherein the second interconnect comprises copper; a second layer on the second interconnect, wherein the second layer comprises nickel; a first electrical pathway in the package substrate, wherein the first electrical pathway is laterally spaced from a first side of the bridge, and wherein the first electrical pathway extends through the dielectric layer; a second electrical pathway in the package substrate, wherein the second electrical pathway is laterally spaced from a second side of the bridge, and wherein the second electrical pathway extends through the dielectric layer; a first die electrically coupled to the first interconnect and to the first electrical pathway; and a second die electrically coupled to the second interconnect and to the second electrical pathway.

9 . The IC assembly of claim 8 , wherein the first die is a processor and the second die is a memory.

10 . The IC assembly of claim 8 , wherein the first die is an application specific integrated circuit and the second die is a memory.

11 . The IC assembly of claim 8 , wherein the dielectric layer is in contact with the bridge.

12 . The IC assembly of claim 8 , wherein the first die and the bridge have a partial lateral overlap, and wherein the second die and the bridge having a partial lateral overlap.

13 . The IC assembly of claim 8 , wherein the bridge is embedded in the cavity of the package substrate.

14 . An IC assembly, comprising:
a plurality of metal lands; an adhesive layer above the plurality of metal lands, wherein the adhesive layer is vertically over a first portion of the plurality of metal lands; a bridge on the adhesive layer, wherein the bridge comprises a silicon substrate; a first dielectric layer laterally adjacent to the adhesive layer and the bridge, the first dielectric layer vertically over a second portion of the plurality of metal lands; a first electrical pathway in the first dielectric layer, wherein the first electrical pathway is laterally spaced from a first side of the bridge, and wherein the first electrical pathway is coupled to a first one of the second portion of the plurality of metal lands; a second electrical pathway in the first dielectric layer, wherein the second electrical pathway is laterally spaced from a second side of the bridge, the second side laterally opposite the first side, and wherein the second electrical pathway is coupled to a second one of the second portion of the plurality of metal lands; a second dielectric layer over the first dielectric layer and over the bridge; a first interconnect over the bridge and electrically coupled to the bridge, the first interconnect in the second dielectric layer, wherein the first interconnect comprises copper; a first layer on the first interconnect, wherein the first layer comprises nickel; a second interconnect over the bridge and electrically coupled to the bridge, the second interconnect in the second dielectric layer, wherein the second interconnect comprises copper; a second layer on the second interconnect, wherein the second layer comprises nickel; a first die electrically coupled to the first interconnect and to the first electrical pathway; and a second die electrically coupled to the second interconnect and to the second electrical pathway.

15 . The IC assembly of claim 14 , further comprising:
a plurality of solder balls beneath the plurality of metal lands, wherein individual ones of the plurality of solder balls are on a corresponding one of the plurality of metal lands.

16 . The IC assembly of claim 14 , wherein the first dielectric layer is in contact with the bridge and with the adhesive layer.

17 . The IC assembly of claim 14 , wherein the first die is a processor and the second die is a memory.

18 . The IC assembly of claim 14 , wherein the first die is an application specific integrated circuit and the second die is a memory.

19 . The IC assembly of claim 14 , wherein the first die and the bridge have a partial lateral overlap, and wherein the second die and the bridge have a partial lateral overlap.

20 . The IC assembly of claim 14 , wherein the bridge is embedded in the cavity of the package substrate.

Assignees

• Intel Corp

Inventors

• Liu Yueli
• Zhang Qinglei
• Schuckman Amanda E
• Zhang Rui

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title