Pocketed copper in first layer interconnect and method

Patent metadata

Field	Value
Publication number	US-2024006291-A1
Application number	US-202217855961-A
Country	US
Kind code	A1
Filing date	Jul 1, 2022
Priority date	Jul 1, 2022
Publication date	Jan 4, 2024
Grant date	—

Abstract

A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

First claim

What is claimed is:

1 . A substrate package comprising:
a substrate comprised of buildup layers; a layer connected to the substrate and including a pocketed region, the layer including silicon and nitrogen, the pocketed region including a first portion thinner than a second portion extending from the first portion; and a solder ball encapsulated within the pocketed region.

2 . The substrate package of claim 1 , wherein the substrate package does not include a solder resist layer.

3 . The substrate package of claim 1 , wherein the solder ball is attached into a pocketed pad within the pocketed region.

4 . The substrate package of claim 3 , wherein the pocketed pad comprises copper.

5 . The substrate package of claim 3 , wherein an intermetallic layer is provided between the solder ball and the pocketed pad.

6 . The substrate package of claim 1 , wherein the layer comprises silicon nitride (SiNx).

7 . The substrate package of claim 1 , wherein the pocketed region includes a surface finish layer.

8 . The substrate package of claim 7 , wherein the surface finish layer comprises at least one of electroless nickel/electroless palladium/immersion gold (ENEPIG), electroless nickel immersion gold (ENIG), or organic solderability preservative (OSP).

9 . An electronic device comprising:
a substrate package comprising:
a substrate comprised of buildup layers;
a passivating layer connected to the substrate and including a pocketed region, the pocketed region including a first portion thinner than a second portion extending from the first portion;
a solder ball encapsulated within the pocketed region; and
an integrated circuit mounted to the substrate package.

10 . The electronic device of claim 9 , wherein the substrate package includes surface routed high speed input/output (HSIO) comprised of copper traces.

11 . The electronic device of claim 9 , wherein the substrate package does not include a solder resist layer.

12 . The electronic device of claim 9 , wherein the solder ball is attached into a pocketed pad within the pocketed region.

13 . The electronic device of claim 12 , wherein the pocketed pad comprises copper.

14 . The electronic device of claim 12 , wherein an intermetallic layer is provided between the solder ball and the pocketed pad.

15 . The electronic device of claim 9 , wherein the passivating layer is comprised of a silicon nitride (SiNx) film.

16 . The electronic device of claim 9 , wherein the pocketed region includes a surface finish layer.

17 . A method of manufacture of a substrate package, the method comprising:
forming a substrate comprised of buildup layers; forming a passivating layer connected to the substrate and including a pocketed region, the pocketed region including a first portion thinner than a second portion extending from the first portion; and encapsulating a solder ball within the pocketed region.

18 . The method of claim 17 , further comprising forming the pocketed region by etching an area into a copper pad.

19 . The method of claim 18 , further comprising attaching the solder ball to a pocketed pad within the pocketed region.

20 . The method of claim 17 , wherein the passivating layer is comprised of a silicon nitride (SiNx) film and whereon the method further comprising providing a surface finish layer over the pocketed region, the surface finish layer comprising at least one of electroless nickel/electroless palladium/immersion gold (ENEPIG), electroless nickel immersion gold (ENIG), or organic solderability preservative (OSP).

Assignees

• Intel Corp

Inventors

• Nad Suddhasattwa
• Ecton Jeremy D
• Marin Brandon C
• Pietambaram Srinivas Venkata Ramanuja
• Duan Gang
• Steill Jason
• Yang Yi
• Wall Marcel Arlan

Classifications

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title