Multi-pathway routing via through hole

Patent metadata

Field	Value
Publication number	US-2023420298-A1
Application number	US-202217851999-A
Country	US
Kind code	A1
Filing date	Jun 28, 2022
Priority date	Jun 28, 2022
Publication date	Dec 28, 2023
Grant date	—

Abstract

An electronic device comprises a substrate layer comprising a first side and an opposing second side, a through hole passing through the substrate layer between the first side and the second side, a first electrical pathway passing from a first position on the first side of the substrate layer, through a first portion of the through hole, to a first corresponding position on the second side of the substrate layer, a second electrical pathway passing from a second position on the first side of the substrate layer, through a second portion of the through hole, to a corresponding second position on the second side of the substrate layer, and an insulation layer between the first electrical pathway and the second electrical pathway within the through hole, wherein the insulation layer electrically isolates the first electrical pathway from the second electrical pathway.

First claim

1 . An electronic device comprising:
a substrate layer comprising a first side and an opposing second side; a through hole passing through the substrate layer between the first side and the second side; a first electrical pathway passing from a first position on the first side of the substrate layer, through a first portion of the through hole, to a first corresponding position on the second side of the substrate layer; a second electrical pathway passing from a second position on the first side of the substrate layer, through a second portion of the through hole, to a corresponding second position on the second side of the substrate layer; and an insulation layer between the first electrical pathway and the second electrical pathway within the through hole, wherein the insulation layer electrically isolates the first electrical pathway from the second electrical pathway.

2 . The electronic device of claim 1 , wherein the first electrical pathway and the second electrical pathway are each configured to carry an electrical signal from the first side to the second side of the substrate layer or to act as a ground between the first side and the second side of the substrate layer or are configured to carry electrical power from the first side to the second side of the substrate layer.

3 . The electronic device of claim 1 , wherein the first electrical pathway is configured to carry an electrical signal from the first side to the second side of the substrate layer and the second electrical pathway is configured as an electrical ground between the first side and the second side of the substrate layer.

4 . The electronic device of claim 1 , wherein the first electrical pathway covers at least a portion of an interior bore surface of the through hole.

5 . The electronic device of claim 1 , wherein the first portion of the through hole, the second portion of the through hole, and the insulation layer within the through hole are coaxial and concentric.

6 . The electronic device of claim 5 , wherein the first portion of the through hole is proximate to a central axis of the through hole and the second portion of the through hole is proximate to an outer circumference of the through hole.

7 . The electronic device of claim 6 , wherein a diameter of the first portion of the through hole is from about 10 micrometers to about 40 micrometers.

8 . The electronic device of claim 6 , wherein an axial thickness of the insulation layer is from about 5 micrometers to about 40 micrometers.

9 . The electronic device of claim 6 , wherein the through hole has a total diameter of from about 50 micrometers to about 150 micrometers.

10 . The electronic device of claim 1 , wherein the insulation layer covers at least a portion of the first electrical pathway on the first side of the substrate layer.

11 . The electronic device of claim 1 , further comprising a second insulation layer covering at least a portion of the second electrical pathway on the first side of the substrate layer.

12 . The electronic device of claim 1 , further comprising a build-up layer deposited over at least a portion of the first electrical pathway, over at least a portion of the second electrical pathway, or over at least a portion of the first electrical pathway and over at least a portion of the second electrical pathway on the first side of the substrate layer.

13 . The electronic device of claim 12 , further comprising a via through the build-up layer that exposes an outer surface of the first electrical pathway or of the second electrical pathway.

14 . The electronic device of claim 1 , wherein the insulation layer comprises silicon and nitrogen.

15 . An electronic package comprising:
a package substrate; a semiconductor die coupled to the package substrate, the semiconductor die comprising:
a substrate layer comprising a first side and an opposing second side;
a through hole passing through the substrate layer between the first side and the second side;
a first electrical pathway passing from a first position on the first side of the substrate layer, through a first portion of the through hole, to a first corresponding position on the second side of the substrate layer;
a second electrical pathway passing from a second position on the first side of the substrate layer, through a second portion of the through hole, to a corresponding second position on the second side of the substrate layer; and
an insulation layer between the first electrical pathway and the second electrical pathway within the through hole, wherein the insulation layer electrically isolates the first electrical pathway from the second electrical pathway

16 . The electronic package of claim 15 , wherein the first electrical pathway is configured to carry an electrical signal from the first side to the second side of the substrate layer and the second electrical pathway is configured as an electrical ground between the first side and the second side of the substrate layer.

17 . The electronic package of claim 15 , wherein the first portion of the through hole, the second portion of the through hole, and the insulation layer within the through hole are coaxial and concentric.

18 . The electronic package of claim 15 , wherein the semiconductor die further comprises a second insulation layer covering at least a portion of the second electrical pathway on the first side of the substrate layer.

19 . The electronic package of claim 15 , wherein the insulation layer comprises silicon and nitrogen.

20 . A method comprising the steps of:
providing or receiving a substrate layer, the substrate layer including a first side, an opposing second side, and a through hole passing through the substrate layer from the first side to the second side; depositing a first conductive material onto the substrate layer to form a first electrical pathway, wherein the first electrical pathway passes from a first position on the first side of the substrate layer, through a first portion of the through hole, to a first corresponding position on the second side of the substrate layer; depositing a first insulating material in contact with the first electrical pathway to form a first insulation layer that electrically isolates the first electrical pathway from a second portion of the through hole; and depositing a second conductive material onto the substrate layer to form a second electrical pathway, wherein the second electrical pathway passes from a second position on the first side of the substrate layer, through the second portion of the through hole, to a corresponding second position on the second side of the substrate layer.

21 . The method of claim 20 , further comprising depositing a second insulating material onto at least a portion of the second electrical pathway.

22 . The method of claim 20 , further comprising depositing a build-up layer onto at least a portion of the first electrical pathway on the first side of the substrate layer, or onto at least a portion of the second electrical pathway on the first side of the substrate layer, or onto at least a portion of the first electrical pathway and onto at least a portion of the second electrical pathway on the first side of the substrate layer.

23 . The method of claim 20 , further comprising forming a first via through the build-up layer to provide a first electrical connection to the first electrical pathway, or a second via through the build-up layer to provide a sec

Assignees

• Intel Corp

Inventors

• Nad Suddhasattwa
• Geyik Cemil Serdar
• Sun Jiwei
• Steill Jason

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title