Backside Deep Trench Capacitor and Inductor Structures

Patent metadata

Field	Value
Publication number	US-2024213139-A1
Application number	US-202218087484-A
Country	US
Kind code	A1
Filing date	Dec 22, 2022
Priority date	Dec 22, 2022
Publication date	Jun 27, 2024
Grant date	—

Abstract

Single-chip solutions that result in high capacitance and/or inductance densities. Embodiments provide relatively large capacitance and/or inductance values for applications utilizing DC and/or sub-KHz signals up to RF signals. Embodiments may include an integrated circuit having a substrate having a backside, a substructure formed on the substrate, and a superstructure formed on the substructure and having a metallization layer, the integrated circuit further including at least one backside deep trench capacitor structure including: one or more trenches formed in the backside of the substrate and lined with a first conductive layer, a dielectric, and a second conductive layer; a first electrical connection between the first conductive layer and a first portion of the metallization layer; and a second electrical connection between the second conductive layer and a second portion of the metallization layer. Embodiments may also include an integrated circuit having at least one backside deep trench capacitor structure.

First claim

1 . An integrated circuit having a substrate having a backside, a substructure formed on the substrate, and a superstructure formed on the substructure and having a metallization layer, the integrated circuit further including at least one backside deep trench capacitor structure including:
(a) one or more trenches formed in the backside of the substrate and lined with a first conductive layer, a dielectric, and a second conductive layer; (b) a first electrical connection between the first conductive layer and a first portion of the metallization layer; and (c) a second electrical connection between the second conductive layer and a second portion of the metallization layer.

2 . The invention of claim 1 , wherein at least one of the first electrical connection or the second electrical connection is a through-silicon via.

3 . The invention of claim 1 , wherein at least one of the one or more trenches is formed from the backside of the substrate and through the substrate to the first portion of the metallization layer.

4 . The invention of claim 1 , wherein the second electrical connection is formed from a capped connector trench.

5 . The invention of claim 1 , wherein the first conductive layer includes a conductive region of the substrate around at least one of the one or more trenches.

6 . The invention of claim 5 , wherein the second electrical connection is formed from a connector trench.

7 . An integrated circuit having a substrate having a backside, a substructure formed on the substrate, and a superstructure formed on the substructure and having a metallization layer, the integrated circuit further including at least one backside deep trench capacitor structure including:
(a) one or more trenches formed in the backside of the substrate and lined with a first conductive layer, a dielectric, and a second conductive layer, wherein the first conductive layer of at least one of the one or more trenches is in electrical contact with a corresponding portion of the metallization layer; and (b) a capped connector trench formed in the backside of the substrate and lined with a first conductive layer, a dielectric, and a second conductive layer, wherein the first conductive layer and the second conductive layer are shorted together and (1) in electrical contact with the second conductive layer of the one or more trenches, and (2) in electrical contact with an associated portion of the metallization layer.

8 . A method of making at least one backside deep trench capacitor structure in an integrated circuit having a substrate having a backside, a substructure formed on the substrate, and a superstructure formed on the substructure and having a metallization layer, the method including:
(a) forming one or more trenches in the backside of the substrate; (b) lining at least one of the one or more trenches with a first conductive layer, a dielectric, and a second conductive layer; (c) forming a first electrical connection between the first conductive layer and a first portion of the metallization layer; and (d) forming a second electrical connection between the second conductive layer and a second portion of the metallization layer.

9 . The method of claim 8 , wherein at least one of the first electrical connection or the second electrical connection is a through-silicon via.

10 . The method of claim 8 , wherein at least one of the one or more trenches is formed from the backside of the substrate and through the substrate to the first portion of the metallization layer.

11 . The method of claim 8 , further including forming the second electrical connection as a capped connector trench.

12 . The method of claim 8 , wherein the first conductive layer includes a conductive region of the substrate around at least one of the one or more trenches.

13 . The method of claim 12 , further including forming the second electrical connection as a connector trench.

14 . The method of claim 8 , further including mounting the integrated circuit on another structure before making the at least one backside deep trench capacitor structure.

15 . The method of claim 14 , wherein the other structure is one of an interposer or laminate.

16 . The method of claim 14 , wherein the other structure a second integrated circuit.

17 .- 21 . (canceled)

Assignees

• Psemi Corp

Inventors

• Ray Shishir
• Kumar Anil
• Goktepeli Sinan
• Kouassi Kouassi Sebastien

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title