Integrated circuits and manufacturing methods thereof

Patent metadata

Field	Value
Publication number	US-2023197723-A1
Application number	US-202318168065-A
Country	US
Kind code	A1
Filing date	Feb 13, 2023
Priority date	May 26, 2010
Publication date	Jun 22, 2023
Grant date	—

Abstract

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, comprising:
forming a first diffusion area and a second diffusion area in a substrate, wherein an isolation region extends from the first diffusion area to the second diffusion area; forming a first drain region and a first source region in the first diffusion area, wherein the first drain region and the first source region are doped with a first dopant type; forming a second drain region and a second source region in the second diffusion area, wherein the second drain region and the second source region are doped with a second dopant type; providing a gate electrode extending from over the first diffusion area and between the first drain region and the first source region to over the second diffusion area and between the second drain region and the second source region; depositing a dielectric layer adjacent the gate electrode and over the first diffusion area, the second diffusion area and the isolation region; etching an opening in the dielectric layer, wherein the opening contiguously extends from over the first drain region to over the second drain region, wherein the opening exposes a surface of the isolation region between the first drain region and the second drain region; depositing a first metallic structure over the first drain region in the opening and a second metallic structure over the second drain region in the opening, wherein a gap extends over the isolation region between the first metallic structure and the second metallic structure; and depositing a third metallic structure over the first metallic structure, over the second metallic structure, and extending to the surface of the isolation region in the gap.

2 . The method of claim 1 , wherein the forming the second drain region includes epitaxially growing the second drain region such that the second drain region is higher than a top surface of the isolation region.

3 . The method of claim 1 , further comprising:
after the etching the opening in the dielectric layer, forming silicide regions on the first drain region and the second drain region.

4 . The method of claim 1 , wherein the depositing the third metallic structure includes depositing copper.

5 . The method of claim 4 , wherein the depositing the first metallic structure and the second metallic structure includes depositing tungsten.

6 . The method of claim 1 , further comprising:
depositing an etch stop layer over the gate electrode prior to etching the opening.

7 . The method of claim 6 , wherein after etching the opening, a top surface of the etch stop layer over the gate electrode is exposed.

8 . The method of claim 1 , wherein the depositing the third metallic structure includes forming an interface between the third metallic structure and a sidewall of each of the first metallic structure and the second metallic structure concurrently.

9 . A method of fabricating a semiconductor device, comprising:
forming a first diffusion area and a second diffusion area in a substrate, wherein an isolation region extends from the first diffusion area to the second diffusion area; forming a first source/drain region in the first diffusion area and a second source/drain region in the second diffusion area; providing a gate electrode extending in a routing direction from over the first diffusion area to over the second diffusion area, wherein the first source/drain region and the second source/drain region are disposed on a first side of the gate electrode in a top view; etching an opening in a dielectric layer over the substrate, wherein the opening contiguously extends from over the first drain region to over the second drain region, wherein the opening exposes a surface of the isolation region between the first source/drain region and the second source/drain region; depositing a first metallic structure over the first drain region in the opening and a second metallic structure over the second drain region in the opening, wherein a gap extends over the isolation region between the first metallic structure and the second metallic structure; and depositing another dielectric layer over the gate electrode after depositing the first metallic structure and the second metallic structure; after depositing the another dielectric layer, forming another opening in the another dielectric layer, wherein the another opening extends from over the first metallic structure to over the second metallic structure and exposes a sidewall of the first metallic structure and a sidewall of the second metallic structure; and depositing a third metallic structure in the another opening, wherein the third metallic structure has a length greater than a width, the length extending in the routing direction.

10 . The method of claim 9 , wherein the another opening in the another dielectric layer extends to a surface of the isolation region.

11 . The method of claim 10 , wherein the surface of the isolation region extends between the first metallic structure and the second metallic structure.

12 . The method of claim 10 , wherein depositing the third metallic structure includes depositing a first composition on the surface of the isolation region.

13 . The method of claim 12 , wherein the first composition is copper.

14 . The method of claim 13 , wherein the depositing the first metallic structure and the second metallic structure includes depositing a second composition different than the first composition.

15 . The method of claim 9 , wherein the forming another opening exposes a top surface of the first metallic structure and a top surface of the second metallic structure, wherein the sidewall of the first metallic structure extends from the top surface of the first metallic structure and the sidewall of the second metallic structure extends from the top surface of the second metallic structure.

16 . A method of fabricating a semiconductor device, comprising:
forming a first diffusion area and a second diffusion area in a substrate, wherein an isolation region extends from the first diffusion area to the second diffusion area; forming a first source/drain region in the first diffusion area and a second source/drain region in the second diffusion area; forming a first dielectric layer over the first source/drain region and the second source/drain region and an etch stop layer over the first dielectric layer; providing an opening in the first dielectric layer and the etch stop layer, wherein the opening extends to the isolation region; depositing a first metallic structure over the first source/drain region in the opening and a second metallic structure over the second source/drain region in the opening, wherein after the depositing the first metallic structure and the second metallic structure a gap between the first metallic structure and the second metallic structure; and depositing a third metallic structure in the gap.

17 . The method of claim 16 , wherein the forming the etch stop layer includes forming an upper surface of the etch stop layer coplanar with an upper surface of the first metallic structure.

18 . The method of claim 16 , wherein depositing the first metallic structure deposits a conductive material directly on a sidewall of the etch stop layer and a sidewall of the first dielectric layer.

19 . The method of claim 16 , wherein the depositing the third metallic structure includes depositing a conductive material directly on the isolation region.

20 . The method of claim 19 ,

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Keshavarzi Ali
• Guo Ta-Pen
• Sung Shu-Hui
• Tseng Hsiang-Jen
• Lin Shyue-Shyh
• Lu Lee-Chung
• Wu Chung-Cheng
• Tien Li-Chun
• Yang Jung-Chan
• Chen ting yu
• Cao Min
• Hou Yung-Chin

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L29/4238

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic

• H01L23/485

  Electricity · mapped topic

• H01L27/092 Primary

  Electricity · mapped topic