Through level vias and methods of formation thereof

Patent metadata

Field	Value
Publication number	US-9330974-B2
Application number	US-91349710-A
Country	US
Kind code	B2
Filing date	Oct 27, 2010
Priority date	Oct 27, 2010
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

In one embodiment, a semiconductor device includes a first metal line disposed in a first metal level above a substrate. A second metal line is disposed in a second metal level disposed over the first metal level. A third metal line is disposed in a third metal level disposed over the second metal level. A through level via contacts the first metal line and the third metal line.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first metal line disposed in a first metal level above a substrate;
a second metal line disposed in a second metal level disposed over the first metal level, the second metal line separated from the first metal line by a first via level;
a third metal line disposed in a third metal level disposed over the second metal level, the third metal line separated from the second metal line by a second via level, wherein the second via level is separated from the first via level by the second metal level, wherein the first metal level, the second metal level, the third metal level, the first via level, and the second via level are at different vertical levels from the substrate in a semiconductor device comprising three metal level and two via levels over the substrate; and
a single continuous through level via contacting the first metal line and the third metal line, wherein the through level via has a first surface contacting the first metal line and a second surface contacting the third metal line, wherein the first surface is below the second metal line, wherein the second surface is above the second metal line, and wherein the first and the second surfaces are parallel to a major surface of the substrate, wherein the through level via extends completely through the first via level to the first metal line and further extends completely through the second via level to the third metal line,
wherein the single continuous through level via comprises a first portion of a metal liner, wherein the third metal line comprises a second portion of the metal liner, wherein the first portion and the second portion are part of the same continuous metal liner, wherein the first portion of the metal liner surrounds sidewalls of the through level via in the first via level and the second via level and is disposed at the first surface contacting the first metal line, the second portion of the metal liner surrounds sidewalls of the third metal line.

2. The device of claim 1 , wherein the first metal line is disposed in a first inter-level dielectric layer, wherein the second metal line is disposed in a second inter-level dielectric layer; and wherein the third metal line is disposed in a third inter-level dielectric.

3. The device of claim 1 , wherein the third metal line and the through level via comprise copper.

4. The device of claim 3 , wherein the second surface of the through level via and a bottom surface of the third metal line comprise copper.

5. The device of claim 1 , further comprising:
a fourth metal line disposed in a fourth metal level disposed over the third metal level, the fourth metal line separated from the third metal line by a third via level; and
a second through level via contacting the first metal line and the fourth metal line, the second through level via extending through the first via level, the second via level, and the third via level.

6. The device of claim 1 , further comprising:
a contact region on a surface of the substrate; and
a second through level via contacting the second metal line and the contact region.

7. The device of claim 1 , further comprising:
a contact region on a surface of the substrate; and
a second through level via contacting the third metal line and the contact region.

8. A method of forming a semiconductor device, the method comprising:
forming a first metal level above a substrate, the first metal level comprising a first metal line;
forming a second metal level over the first metal level, the second metal level comprising a second metal line, the second metal line separated from the first metal line by a first via level;
forming a third metal level over the second metal level, the third metal level comprising a third metal line, the third metal line separated from the second metal line by a second via level; and
forming a single continuous through level via contacting the first metal line and the third metal line, wherein the through level via has a first surface contacting the first metal line and a second surface contacting the third metal line, wherein the first surface is below the second metal line, wherein the second surface is above the second metal line, and wherein the first and the second surfaces are parallel to a major surface of the substrate, wherein the through level via extends completely through the first via level to the first metal line and further extends completely through the second via level to the third metal line, wherein forming the single continuous through level via comprises forming a first portion of a metal liner, wherein forming the third metal level comprises forming a second portion of the metal liner, wherein the first portion and the second portion are formed in a single process step to form a continuous metal liner, wherein the first portion of the metal liner surrounds sidewalls of the through level via in the first via level and the second via level and is disposed at the first surface contacting the first metal line, the second portion of the metal liner surrounds sidewalls of the third metal line, wherein the second via level is separated from the first via level by the second metal level, and wherein the first metal level, the second metal level, the third metal level, the first via level, and the second via level are at different vertical levels from the substrate in a semiconductor device comprising three metal level and two via levels over the substrate.

9. The method of claim 8 , wherein the through level via and the third metal line are filled using the same process.

10. The method of claim 9 , wherein forming the through level via comprises:
forming a through via opening;
forming a metal line opening aligned over the through via opening; and
filling the through via opening and the metal line opening with a fill metal.

11. The method of claim 8 , wherein forming the through level via comprises:
depositing a metal liner over a through via opening; and
depositing a fill metal over the metal liner.

12. A method of forming a semiconductor device, the method comprising:
forming a first inter-level dielectric layer comprising a first metal line over a substrate;
forming a second inter-level dielectric layer comprising a second metal line over the first inter-level dielectric layer, the second metal line separated from the first metal line by a first via level;
forming a third inter-level dielectric layer over the second inter-level dielectric layer;
forming a through via opening in the second and the third inter-level dielectric layers;
forming a pattern for a third metal line in the third inter-level dielectric layer, the third metal line separated from the second metal line by a second via level; and
filling the through via opening and the pattern for the third metal line with a conductive material to form a single continuous via extending from a first surface to an opposite second surface and the third metal line, wherein the first surface is above the second inter-level dielectric layer, wherein the second surface is below the second inter-level dielectric layer, and wherein the first and the second surfaces are parallel to a major surface of the substrate, wherein the single continuous via extends completely through the first via level to the first metal line and further extends completely through the second via level to the third metal line, wherein filling the through via opening and the pattern for the third metal line comprises forming a first portion and a second portion of a metal liner, wherein the first portion and the second portion are formed in a single process step to form a continuous metal liner, wher

Assignees

• Kim Sunoo
• Pallachalil Muhammed Shafi
• Chae Moosung
• Kaltalioglu Erdem
• Infineon Technologies Ag

Inventors

• Kim Sunoo
• Pallachalil Muhammed Shafi
• Chae Moosung
• Kaltalioglu Erdem

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title