Method of manufacturing semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-2023187482-A1
Application number	US-202217660461-A
Country	US
Kind code	A1
Filing date	Apr 25, 2022
Priority date	Dec 13, 2021
Publication date	Jun 15, 2023
Grant date	—

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: forming a first stacked structure, and forming a first target structure in the first stacked structure; and forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure in the second stacked structure.

First claim

1 . A method of manufacturing a semiconductor structure, comprising: forming a first stacked structure, and forming a first target structure in the first stacked structure; and forming a second stacked structure on the first stacked structure, and forming a second target structure in contact with the first target structure in the second stacked structure.

2 . The method of manufacturing a semiconductor structure according to claim 1 , wherein the forming a first stacked structure, and forming a first target structure in the first stacked structure comprises:
sequentially forming a first sacrificial layer and a first support layer; patterning the first sacrificial layer and the first support layer, and forming a first target pattern hole in the first stacked structure; and forming the first target structure in the first target pattern hole.

3 . The method of manufacturing a semiconductor structure according to claim 2 , wherein the forming the first target structure in the first target pattern hole comprises:
depositing a conductive material in the first target pattern hole and forming the first target structure, a top surface of the first target structure being not higher than a top surface of the first support layer.

4 . The method of manufacturing a semiconductor structure according to claim 3 , wherein the depositing a conductive material in the first target pattern hole and forming the first target structure comprises:
depositing the conductive material to fill the first target pattern hole and cover a top surface of the first stacked structure, and forming a first conductive layer; and etching back and removing a part of the first conductive layer covering the top surface of the first stacked structure, and forming the first target structure.

5 . The method of manufacturing a semiconductor structure according to claim 3 , wherein a material of the first target structure is a compound formed from one or both of a metal nitride or a metal silicide.

6 . The method of manufacturing a semiconductor structure according to claim 2 , wherein the forming a second stacked structure, and forming a second target structure in the second stacked structure comprises:
sequentially forming a second support layer and a dielectric layer on the first stacked structure; patterning the second support layer and the dielectric layer, and forming a second target pattern hole in the second stacked structure, the second target pattern hole at least exposing a part of the first target structure; and forming the second target structure in the second target pattern hole.

7 . The method of manufacturing a semiconductor structure according to claim 6 , wherein the forming a dielectric layer comprises:
forming a second sacrificial layer on the second support layer, and forming a third sacrificial layer on the second sacrificial layer.

8 . The method of manufacturing a semiconductor structure according to claim 6 , wherein the forming the second target structure in the second target pattern hole comprises:
depositing a conductive material in the second target pattern hole and forming the second target structure, the second target structure covering the part of the first target structure exposed.

9 . The method of manufacturing a semiconductor structure according to claim 8 , wherein the depositing a conductive material in the second target pattern hole and forming the second target structure comprises:
depositing the conductive material to fill the second target pattern hole and cover a top surface of the second stacked structure, and forming a second conductive layer; and etching back and removing a part of the second conductive layer covering the top surface of the second stacked structure, and forming the second target structure.

10 . The method of manufacturing a semiconductor structure according to claim 8 , wherein a material of the second target structure is a compound formed from one or both of a metal nitride or a metal silicide.

11 . The method of manufacturing a semiconductor structure according to claim 1 , wherein a material of the first target structure is the same as a material of the second target structure, or the material of the first target structure is different with the material of the second target structure.

12 . The method of manufacturing a semiconductor structure according to claim 7 , further comprising:
removing a part of the second stacked structure and a part of the first stacked structure, a remaining part of the second stacked structure and a remaining part of the first stacked structure forming a support structure.

13 . The method of manufacturing a semiconductor structure according to claim 12 , wherein the removing a part of the second stacked structure and a part of the first stacked structure comprises:
forming a first mask layer, the first mask layer covering a part of a top surface of the second stacked structure and a part of a top surface of the second target structure; sequentially removing a part of the third sacrificial layer, the second sacrificial layer and a part of the second support layer of the second stacked structure based on the first mask layer; and sequentially removing a part of the first support layer and the first sacrificial layer of the first stacked structure based on the first mask layer, wherein a remaining part of the first support layer and a remaining part of the second support layer form the support structure.

14 . The method of manufacturing a semiconductor structure according to claim 1 , comprising:
providing a substrate, the substrate comprising a capacitor contact portion, wherein the first stacked structure is formed on the substrate.

15 . The method of manufacturing a semiconductor structure according to claim 14 , wherein the forming a first target structure in the first stacked structure comprises:
forming the first target structure, the first target structure being in contact with the capacitor contact portion.

16 . The method of manufacturing a semiconductor structure according to claim 1 , further comprising:
forming a dielectric layer, the dielectric layer at least covering an exposed part of a sidewall of the first target structure, an exposed part of a sidewall of the second target structure and a top surface of the second target structure; and forming a top electrode layer, the top electrode layer covering the dielectric layer.

17 . A semiconductor structure, comprising:
a bottom electrode, comprising a first target structure and a second target structure stacked on the first target structure; and a support structure, covering a part of a seam of a connecting surface of the first target structure and the second target structure.

18 . The semiconductor structure according to claim 17 , further comprising:
an upper support layer, provided on a top of the second target structure and covering a part of a sidewall of the second target structure.

19 . The semiconductor structure according to claim 17 , further comprising:
a dielectric layer, at least covering an exposed part of a sidewall of the first target structure, an exposed part of a sidewall of the second target structure, a top surface of the second target structure and the support structure; and a top electrode layer, covering the dielectric layer.

20 . The semiconductor structure according to claim 17 , further comprising:
a substrate, comprising a capacitor contact portion, wherein the first target structure is provided on the capacitor con

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Zuo Mingguang
• Bai Shijie

Classifications

• H10B12/01

  Manufacture or treatment · CPC title

• H01L27/10844

  Electricity · mapped topic

• H01L28/92 Primary

  Electricity · mapped topic

• H10D1/716

  having vertical extensions · CPC title

• H10D1/692

  Electrodes · CPC title